On 4/23/2024 3:51 AM, Theodoros Papavasiliou via gem5-users wrote:
Hello everyone,
I'm running some spec2017 benchmarks on gem5 and I noticed there are some dirty blocks inside the L1 instruction cache.
These blocks are also shared with the L1 data cache.
So, what is a possible explanation for:
1) having dirty blocks in instruction cache and
2) having the same blocks in both L1 data and instruction caches?
System configuration
CPU: O3, clock=3.4GHz
L1D: size=32KiB, assoc=8, latency=2
L1I: size=32KiB, assoc=8, latency=2
L2: size=128KiB, assoc=8, latency=15
No prefetchers
Run for 20 million instructions
I'm using private_l1_private_l2_cache_hierarchy.py
If the program creates or modifies code, then the created / modified
code will be dirty in the L1 data cache. If that code is then executed,
it will be fetched into the L1 instruction cache. It is still dirty in
that it has not yet been written back to main memory. That's one scenario,
though others may be possible.
Regards - Eliot Moss
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