Hi Hoa I tried the 'vlen' option, it worked.
Thanks a lot! Regards, Xiaokang Hoa Nguyen <hoangu...@ucdavis.edu> 于2024年3月28日周四 13:20写道： > Hi Xiaokang, > > You can set the vlen parameter of the RiscvISA object to change the vector > length. > > https://github.com/gem5/gem5/blob/stable/src/arch/riscv/RiscvISA.py#L101 > > Regards, > Hoa Nguyen > > On Wed, Mar 27, 2024, 21:47 Xiaokang Fan via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi all, >> >> I have a question regarding the configuration of vector lengths for the >> RISC-V V extension in Gem5. >> >> >> I know that for ARM SVE, Gem5 provides options such as 'system.sve_vl' >> and 'system.cpu[:].isa[:].sve_vl_se' to set the vector length. However, I >> am curious if there are any analogous settings available for customizing >> the vector length of the RISC-V V extension. >> >> >> I would greatly appreciate any help. >> >> >> Best regards, >> >> >> Xiaokang >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> >
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