Hi All, In the AMD_MOESI protocol, when working with syscall emulation, I run into an issue where the Corepair controller memory port is unconnected, giving me the following message: src/sim/port.cc:62: fatal: system.cp_cntrl0.memory: Unconnected port!
After doing some digging, I was able to understand that the memory port is passed down from the RubyController module. From what I can guage, this meant to be hooked up to the next level of the memory hierarchy, but it also seems as though in the AMD_MOESI setup, that comes with gem5, that the corepair calls to the L3 through the ruby network in/out ports, hence why I could work with it in the memory testing example provided. Now, I am quite stuck figuring out what to do with this port. Do I make an additional connection to L3? Can I tie it off somehow? Is my understanding perhaps wrong? Any and all insight is appreciated, I am quite stuck on this issue. Thanks!
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