Hi all, I'm trying to develop my own coherence protocol that supports multiple outstanding requests.
My questions are as follows: 1. With a cache line at address A marked 'AccessPermission:Busy' in the directory, no copies in the hierarchy, and no related messages in buffers—typically seen during a cold miss awaiting a main memory response—can we anticipate functional access during syscall emulation? 2. If yes, should such a functional access be successful in a correctly implemented protocol? 3. If not, might there be a safeguard mechanism I'm overlooking that prevents this scenario? Thanks for your help! --- Here are more details that you might need: There's a directory in my protocol that functions similarly to MESI_Two_Level-dir.sm <https://github.com/gem5/gem5/blob/stable/src/mem/ruby/protocol/MESI_Two_Level-dir.sm> when it comes to fetching data from its memory port (requestToMemory), where a cache line goes through the transition of I (Read_Write) -> IM (Busy) -> M (Maybe_Stale). I'm encountering a scenario where a functional access is sent to Ruby when the cache line is in IM state, after the request is sent to the main memory and before the main memory sends back the response. This way, the functional access will fail because the line is in a busy state (IM) but nothing is found in the message buffer - and it causes a fatal error. I tried directly constructing a functional access at similar timing using MESI_Two_Level, the same fatal error happens, where such a functional access would fail. Best, Wu
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