Hi Anshul,
My research group has recently released a gem5 modification to support
page walk (and use of TLB) in syscall emulation mode. You can find it at
the following link: https://github.com/mircomannino/gem5/tree/rapido24
The modifications were made only for RISC-V, I don't know which ISA you
are working with.
The changes made are explained in an accepted but not yet published
paper. I will let you know when the paper is available.
Regards,
Mirco Mannino
Il 14/12/23 23:35, Anshul Naithani via gem5-users ha scritto:
Hi,
I implemented my prefetcher design which generates prefetches in the
calculatePrefetch() function by pushing the prefetch addresses into:
std::vector<AddrPriority> &addresses
However, what I found out was that the addresses I pushed were Page
crossing (so I added MMU to dcache and l2cache in the
configs/common/CacheConfig.py) and then had no physical address. Due
to no translations I observed that all such prefetches were ultimately
rendered useless as it took a ridiculously long time for the
prefetch''s virtual addresses (in prefetch queue) to get translated to
physical address.
I'm using configs/deprecated/example/se.py and I wanted to add a TLB
hierarchy for my gem5 run. However I could not find any
document/example on how to do so. If anyone has already set up their
TLB, do let me know.
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