On 12/1/2023 6:24 PM, zahra moein via gem5-users wrote:
Thank you for your response.
I would like to seek further clarification regarding the parameter
RecvTimingResp:
void BaseCache::recvTimingResp(PacketPtr pkt)
Could you please confirm if this parameter represents a packet that is received from memory? If it does, I would
appreciate your guidance on how to determine whether this packet is a response to a read miss request in the last-level
cache.
Thank you for your valuable assistance.
It's a packet received from whatever the cache is connected to. If it's the
last level cache, then it should come from the memory bus, which would have
gotten it from memory. But you need to analyze what sort of packet it is, and
the nature of the *request* that resulted in the packet, etc. You should at
least get a sense of the control flow of that function and perhaps of some of
the significant functions it calls.
If the data are headed for this cache, then there will be some place where
they get loaded into a cache block.
I'm not sure you can say with 100% certainty it has to do with a read miss,
though if you look for where read misses generate requests, that may be
helpful. One possibly confounding case is packet arriving because of prefetch
- but I think they should be marked as such.
Btw, another case is when another cache responds, but from the viewpoint of
this cache it will still be a recvTimingResp (at the memory bus, a
recvTimingSnoopResp will be involved).
My intention was to point you where to start understanding the code, well
enough at least, not to indicate the specific code location. (My notion is
that you'll be better off if you study it some and learn more about how it
works (not every detail, since there's a lot of complexity there!), as opposed
to being directed to specific line(s) of code.) Another clue would be where
statistics counters get updated :-) .
It's conceivable that it will be easier to find the data coming from memory
due to read misses by looking at packets coming to the memory bus from the
memory controller(s). (I assume you're not interested in data arriving from
I/O devices.)
If you end up really stuck, I may be able to find time to take a look.
HTH -- EM
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