Hi Gunjan, I am not an expert at this. I found some stats that represent cache miss latency and might be helpful: overallMisses::processor.cores.core.inst, overallMisses::total, demandMissLatency::processor.cores.core.inst, demandMissLatency::total, overallMissLatency::processor.cores.core.inst, overallMissLatency::total, demandAvgMissLatency::processor.cores.core.inst, demandAvgMissLatency::total, overallAvgMissLatency::processor.cores.core.inst, and overallAvgMissLatency::total.
A note the above mentioned stats would be followed by a cache hierarchy type for example the complete stat would look like: board.cache_hierarchy.l1icaches.overallMissLatency::total or board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total. Regards, Harshil Patel On Fri, Nov 10, 2023 at 8:02 AM Gunjan Dhanuka via gem5-users < gem5-users@gem5.org> wrote: > I am trying to study the effects on the cache level of a certain attack > that acts on the NoC network level. For this, I want to obtain the L1 Cache > Miss penalty for each core. I looked into the stats.txt file but couldn't > find any stat corresponding to it directly. There is a stat called > l1_cntrl.delayHistogram.mean, I couldn't find the exact meaning of it. Can > someone help here? Thanks in advance > > Regards > Gunjan Dhanuka > Indian Institute of Technology, Guwahati > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org >
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