[gem5-users] Gem5 SE mode with SystemC for RISC-V

[泰。 via gem5-users]

Hello All,

I have been searching for a demonstration or example that showcases the 
integration of Gem5 SE mode with SystemC for the RISC-V architecture.



I am a beginner in Gem5, and I am trying to connect using the following method, 
but I am facing an 'AttributeError: Class StubWorkload has no parameter 
addr_check' error. I don't know how to resolve it.



cd util/tlm
../../build/RISCV/gem5.debug ../../configs/example/se.py    \
--tlm-memory=transactor                 
                    \
--cpu-type=TimingSimpleCPU               
                   \
--num-cpu=1                   
                      
        \
--mem-type=SimpleMemory                 
                    \
--mem-size=512MB                   
                      
   \
--mem-channels=1                   
                      
   \
--cmd=../../tests/test-progs/hello/bin/riscv/linux/hello    \
--caches --l2cache



Does the thread below have a final conclusion and examples in the current 
version of Gem5？

https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64


Best regards,
Zitai
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