I think there is a very minor typo in the documentation on the following page: "https://www.gem5.org/documentation/gem5-stdlib/develop-stdlib-board"; "from .unqiue_board import UniqueBoard" Should instead be: "from .unique_board import UniqueBoard" However, I ended up dropping the "." and using the following: "from unique_board import UniqueBoard"
So good so far. I also followed the wonderful documentation at the following page to get the needed "UniqueCacheHierarchy": "https://www.gem5.org/documentation/gem5-stdlib/develop-own-components-tutorial"; However, when I try to run things, I get the following error: prompt> riscv-gem5 configs/uniqueboard/config.py gem5 Simulator System. https://www.gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 version 22.1.0.0 gem5 compiled Jun 25 2023 08:56:48 gem5 started Jun 25 2023 14:18:54 gem5 executing on lvablnode14, pid 234413 command line: riscv-gem5 configs/uniqueboard/config.py AttributeError: Class UniqueCPU has no parameter core_id At: build/RISCV/python/m5/SimObject.py(913): __setattr__ build/RISCV/python/m5/SimObject.py(768): __init__ build/RISCV/cpu/BaseCPU.py(297): __init__ configs/uniqueboard/uniqueboard.py(19): <module> <frozen importlib._bootstrap>(219): _call_with_frames_removed <frozen importlib._bootstrap_external>(678): exec_module <frozen importlib._bootstrap>(665): _load_unlocked <frozen importlib._bootstrap>(955): _find_and_load_unlocked <frozen importlib._bootstrap>(971): _find_and_load configs/uniqueboard/config.py(1): <module> build/RISCV/python/m5/main.py(597): main The original page ("https://www.gem5.org/documentation/gem5-stdlib/develop-stdlib-board";) mentions that: "BaseCPU objects require a unique core_id to be specified upon construction." However, when I look into the Python source code in "build/RISCV/cpu/BaseCPU.py" I don't see the "core_id" flag being used. This could be passed to the parent class, but that's a "ClockedObject" which probably doesn't care about a "core_id". When I remove the "core_id=0" from the example on the page so the line instead looks like "BaseCPUCore(core = UniqueCPU())", things will work, and I get my "Hello World" output. Thanks again for the wonderful documentation, I think there's just a couple of minor issues in there. Although, I suppose that turned out to help me learn more as I tracked down what the problems were instead of just blindly running already perfect examples. Also, as to my previous questions about getting specific RISC-V core models to test with, it does look like the included CPU models have lots of parameters, so it would likely be possible to just set the right parameters to get the existing models to act like specific CPU cores like "Rocket" or "Boom" cores. There's a lot of fun options to play with, some below from the "config.ini" file which is super helpful. This is just for the minor core; so many options to play with with the out-of-order core model are available. -- I might again ask if there is any preferred way to model cores like "Rocket" or "Boomv3", etc. It seems like someone, somewhere probably has one of the base models configured to look like these real-world examples. I wonder where one might find some of these settings preconfigured. [board.processor.cores.core] type=BaseMinorCPU children=branchPred decoder executeFuncUnits interrupts isa mmu power_state tracer workload branchPred=board.processor.cores.core.branchPred checker=Null clk_domain=board.clk_domain cpu_id=-1 decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=2 decoder=board.processor.cores.core.decoder do_checkpoint_insts=true do_statistics_insts=true enableIdling=true eventq_index=0 executeAllowEarlyMemoryIssue=true executeBranchDelay=1 executeCommitLimit=2 executeCycleInput=true executeFuncUnits=board.processor.cores.core.executeFuncUnits executeInputBufferSize=7 executeInputWidth=2 executeIssueLimit=2 executeLSQMaxStoreBufferStoresPerCycle=2 executeLSQRequestsQueueSize=1 executeLSQStoreBufferSize=5 executeLSQTransfersQueueSize=2 executeMaxAccessesInMemory=2 [...] Thanks much, ~Aaron Vose
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