I'm sorry, I agree that the dirty bit is a cache concept. I meant that the data would get written at the address after an introduced delay. I'm trying to implement the suggested solutions and I'll give an update on it soon.
On Sat, Jun 10, 2023 at 2:56 PM Eliot Moss <m...@cs.umass.edu> wrote: > On 6/10/2023 2:32 PM, Vincent Abraham via gem5-users wrote: > > I'm extremely sorry if I worded my question incorrectly. I'm actually > trying to introduce a delay > > whenever a read/write request happens in the main memory. For example, > in a memory write, the data > > would only be flagged as dirty after a 10ns delay. > > I'm trying to understand what you're talking about, > but having some difficulty. "Flagged as dirty" is a > *cache* concept, not a main memory concept, AFAIK. > There are a variety of queues and parameters in the > memory controllers. If you find the right place to > delay something, you can simply add some more time > to the schedule time for the next event in the > processing pipeline. Or, with more coding, insert > an additional internal queue. > > But what does "flagged as dirty" mean to you? > > Best - E< >
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
