Hi Eliot, I can’t provide you with an assertive answer but I’ve also been looking at CXL recently so here is what I understand so far.
>From a functional perspective, the classic cache system seems able to support >the hierarchical coherency aspects just fine with the coherent Xbar of each >chip connected to a CPU side port of the other chip’s Xbar. The performance >will probably be quite off, though. You could improve on it by implementing a >kind of throttle adapter SimObject that would model the CXL link layer between >the 2 xbars. Snoop performance modeling will remain atomic/blocking just as >with any classic cache configuration. As for Ruby, the goal is further away. AFAIK, no protocols supports hierarchical coherency (home node to home node requests, snoopable home node, etc.). If you don’t care too much about these details, then I would argue that configuring any Ruby protocol as usual and configuring your topology to force traffic through a single link could get you closer to a CXL-style configuration. You could also implement a link adapter/bridge component to model the CXL link layer better. Regards, Gabriel
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