Hi Ayaz,
I cloned the repository from https://github.com/gem5/gem5.git
built with command python3 `which scons` build/X86/gem5.opt -j13
and got warnings
> Warning: Deprecated namespaces are not supported by this compiler.
> Please make sure to check the mailing list for deprecation
> announcements.
> Warning: Couldn't find HDF5 C++ libraries. Disabling HDF5 support.
running with command ./build/X86/gem5.opt --debug-flags=AddrRanges
--debug-file=out configs/experiments/config.py
> gem5 Simulator System. https://www.gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
> gem5 version 22.1.0.0
> gem5 compiled Mar 19 2023 11:59:02
> gem5 started Mar 19 2023 12:15:11
> gem5 executing on ubuntu20, pid 66686
> command line: ./build/X86/gem5.opt --debug-flags=AddrRanges
> --debug-file=out configs/experiments/config.py
> Global frequency set at 1000000000000 ticks per second
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (32768
> Mbytes) does not match the address range assigned (1 Mbytes)
> build/X86/base/statistics.hh:280: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
> 0: system.remote_gdb: listening for remote gdb on port 7000
> Beginning simulation!
> build/X86/sim/simulate.cc:192: info: Entering event queue @ 0. Starting
> simulation...
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
> build/X86/sim/syscall_emul.hh:1014: warn: readlink() called on
> '/proc/self/exe' may yield unexpected results in various settings.
> Returning '/home/chenbo/gem5/configs/experiments/test'
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> build/X86/sim/mem_pool.cc:120: fatal: fatal condition freePages() <= 0
> occurred: Out of memory, please increase size of physical memory.
> Memory Usage: 131532 KBytes
debug file shows the followings
> 0: system.physmem: Creating backing store for range [0:0x100000]
> with size 1048576
> 0: system.physmem: Mapping memory system.memories0 to backing store
> 0: system.physmem: Creating backing store for range
> [0x100000:0x900000] with size 8388608
> 0: system.physmem: Mapping memory system.memories1 to backing store
> 0: system.membus: Received range change from cpu_side_ports
> system.cpu.interrupts.int_responder
> 0: system.membus: Adding range
> [0xa000000000000000:0xa000000000001000] for id 3
> 0: system.membus: Received range change from cpu_side_ports
> system.cpu.interrupts.pio
> 0: system.membus: Adding range
> [0x2000000000000000:0x2000000000001000] for id 2
> 0: system.membus: Received range change from cpu_side_ports
> system.dram_ctrl.port
> 0: system.membus: Adding range [0:0x100000] for id 0
> 0: system.membus: Adding snooping requestor system.cpu.dcache_port
> 0: system.membus: Received range change from cpu_side_ports
> system.nvm_ctrl.port
> 0: system.membus: Got address ranges from all responders
> 0: system.membus: Adding range [0x100000:0x900000] for id 1
> 0: system.membus: Aggregating address ranges
> 0: system.membus: -- Adding range [0:0x100000]
> 0: system.membus: -- Adding range [0x100000:0x900000]
> 0: system.membus: -- Adding range
> [0x2000000000000000:0x2000000000001000]
> 0: system.membus: -- Adding range
> [0xa000000000000000:0xa000000000001000]
the config file and test c source code are attached, and compiled with
command gcc test.c -o test -static
when I swapped the nm_size and fm_size in config.py, no error occured
Ayaz Akram <yazak...@ucdavis.edu> 于2023年3月19日周日 09:29写道：
> Hi Brian,
>
> Can you share the script/configuration that ran into the problem with the
> stable branch? I did a quick test with the traffic generator (with two
> different mem devices) and things seem to work ok on my end.
>
> Thanks,
> -Ayaz
>
> On Sat, Mar 11, 2023 at 9:33 AM Brian Chan via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> it may be a bug of stable branch, after i checkout v21.0.0.0 it runs ok
>>
>> Brian Chan <asd1366464...@gmail.com> 于2023年3月11日周六 02:00写道：
>>
>>> Hello,
>>> I'm trying to connect 2 different memory devices on a membus, it is like
>>> cpu->membus->ctrls, and i set mem ranges to be [AddrRange('1MB'),
>>> AddrRange('1MB', ''8MB')], I get Out of memory, but when i swap the ranges,
>>> it runs ok, it seems only the first memory device is recognized.I'm not
>>> sure if this is expected or i made some mistakes?
>>> Thanks!
>>>
>> _______________________________________________
>> gem5-users mailing list -- gem5-users@gem5.org
>> To unsubscribe send an email to gem5-users-le...@gem5.org
>>
>
#include <stdio.h>
#include <stdlib.h>
void recursive(int depth)
{
int val = depth - 1;
if(depth == 0)
{
printf("end\n");
}
else
{
recursive(depth - 1);
}
}
int main()
{
const int size = 1024; //4k pertimes
for(int i = 0; i < 3*1024 / 4; ++i)
{
int* p = (int*)malloc(sizeof(int) * size);
p[0] = -1;
}
int v = 0;
printf("stack pos %p\n", &v);
int* p = (int*)malloc(1);
printf("heap pos %p\n", p);
printf("Hello\n");
recursive(1000);
return 0;
}
import m5
from m5.objects import *
system = System()
system.clk_domain = SrcClockDomain(
clock = '1GHz',
voltage_domain = VoltageDomain()
)
system.mem_mode = 'timing'
nm_size = 1
fm_size = 8
system.mem_ranges = [AddrRange(Addr(0), Addr(str(nm_size) + "MB")),
AddrRange(Addr(str(nm_size) + "MB"), Addr(str(nm_size + fm_size) + "MB"))]
system.memories = [DDR4_2400_16x4(range=system.mem_ranges[0]),
NVM_2400_1x64(range=system.mem_ranges[1])]
system.dram_ctrl = MemCtrl()
system.dram_ctrl.dram = system.memories[0]
system.nvm_ctrl = MemCtrl()
system.nvm_ctrl.dram = system.memories[1]
system.cpu = TimingSimpleCPU()
system.membus = SystemXBar()
system.cpu.icache_port = system.membus.cpu_side_ports
system.cpu.dcache_port = system.membus.cpu_side_ports
system.dram_ctrl.port = system.membus.mem_side_ports
system.nvm_ctrl.port = system.membus.mem_side_ports
system.cpu.createInterruptController()
# x86 only
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
system.system_port = system.membus.cpu_side_ports
binary = os.path.join(
"/home/chenbo/gem5/"
"configs/experiments/test"
)
system.workload = SEWorkload.init_compatible(binary)
process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()
root = Root(full_system=False, system=system)
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print("Exiting @ tick {} because {}"
.format(m5.curTick(), exit_event.getCause()))
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