Hi Haseung, I am not sure if I have fully understood the question, but I will try to answer based on my understanding (please let me know if I misunderstood). SE mode, on a TLB miss, makes use of the gem5 managed page table for the simulated process instead of modeling a page table walk and I guess that might mean smaller TLB miss latency compared to a full system simulation which uses page table walker and also the OS itself is simulated. Also, as far as I remember there is not an explicit parameter for the tlb miss penalty and in SE mode it might look similar to hit latency. Overall, I think full-system simulation is a better choice if you care about the TLB system latencies.
-Ayaz On Tue, Mar 14, 2023 at 12:21 AM 봉하승 via gem5-users <gem5-users@gem5.org> wrote: > Hi, > > > I’m currently simulating ARM O3CPU through SE mode. > > It was confirmed that generic page fault occurred and was restored in mmu. > > > Does this process affect the entire cycle as a penalty? > > > Regards, > > Haseung > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org >
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