Hi Hoa,

Thank you for your email. I will be focusing on arm SVE as with the current
information it shows much more promising results. If you (or anyone else
;)) know any promising beginning I would be very grateful. Otherwise
(probably in either case), I will work myself through the tutorial.

Cheers,
Alex




On Wed, Mar 8, 2023 at 2:33 AM Hoa Nguyen <hoangu...@ucdavis.edu> wrote:

> Hi Alex,
>
> The answer to your question depends on quite a few factors.
>
> One of them is what are the ISAs do you plan to investigate. As far as I
> know, x86 in gem5 does not support a lot of SIMD extensions. I believe arm
> NEON is pretty well supported in gem5.
>
> In terms of vector length agnostic instructions support, arm SVE is pretty
> well supported too. RISC-V Vector Extension (RVV) 1.0 support is still
> under reviewed. Though there is a RVV 0.7 implementation that is not in
> mainline gem5, and a small RVV 1.0 implementation that supports a small
> number of instructions but supports out-of-order execution.
>
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 7, 2023, 17:15 Procelewski, Alex via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi all,
>> I'm an undergraduate student at the University of Groningen and I will be
>> writing my Bachelor Thesis on automatic vectorization. I have a question
>> about whether I can compile specific apps for gem5?
>>
>> In particular, I want to test how a specific compiled app performs under
>> different circumstances (clock speed, vector sizes...), but for that I
>> would need to be able to run a compiled application. As I'm currently
>> writing my proposal I only had limited time to look through the
>> documentation. I couldn't find any information on this however.
>>
>> I would appreciate it a lot if you could guide me in a direction or give
>> a feasibility on whether this is possible with gem5
>>
>> Kind regards
>> Alex Procelewski
>>
>>
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>
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