Hello,
I wrote the code for a customized network in the mem/ruby/network directory
next to garnet, which doesn't use virtual networks. I am trying to simulate
this network using synthetic traffic. When I tried to run the simulation
for this network after a successful build, I faced a std::vector
out-of-range problem. After putting assertions in place, and some printing,
it turned out that only the constructors of two of the modules I
implemented was being called and the configuration instantiation
(m5.instantiate(args.abs_max_tick)) was unsuccessful, exiting at tick 0
without entering the simulation.
I have trouble pinpointing the problem that obstructs the instantiation.
Could it be that I'm not communicating correctly with controllers, or in
this stage before the simulation, the problem is with how I implemented my
customized network SimObjects?
This is the command line I am running:
===================================================
build/NULL/gem5.opt configs/example/routerless_synth_traffic.py
--network=routerless --num-cpus=16 --num-dirs=16 --eject-links=3
--num-exbs=3 --topology=Routerless_XY --rl-rows=4 --sim-cycles=1000
--synthetic=uniform_random --precision=3 --injectionrate=0.02
--rl-latency=1 --link-latency=1 --link-width-bits=16 --routing-algorithm=0
===================================================
I have attached the configuration script (routerless_synth_traffic.py) and
the topology file (Routerless_XY.py) that I am using, if helpful.
Warm regards,
Ali Karazmoodeh
# Copyright (c) 2016 Georgia Institute of Technology
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Author: Tushar Krishna
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
addToPath('../')
from common import Options
from ruby import Ruby
# Get paths we might need. It's expected this file is in m5/configs/example.
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)
parser = argparse.ArgumentParser()
Options.addNoISAOptions(parser)
parser.add_argument("--synthetic", default="uniform_random",
choices=['uniform_random', 'tornado', 'bit_complement', \
'bit_reverse', 'bit_rotation', 'neighbor', \
'shuffle', 'transpose'])
parser.add_argument("-i", "--injectionrate", type=float, default=0.1,
metavar="I",
help="Injection rate in packets per cycle per node. \
Takes decimal value between 0 to 1 (eg. 0.225). \
Number of digits after 0 depends upon --precision.")
parser.add_argument("--precision", type=int, default=3,
help="Number of digits of precision after decimal point\
for injection rate")
parser.add_argument("--sim-cycles", type=int, default=1000,
help="Number of simulation cycles")
parser.add_argument("--num-packets-max", type=int, default=-1,
help="Stop injecting after --num-packets-max.\
Set to -1 to disable.")
parser.add_argument("--single-sender-id", type=int, default=-1,
help="Only inject from this sender.\
Set to -1 to disable.")
parser.add_argument("--single-dest-id", type=int, default=-1,
help="Only send to this destination.\
Set to -1 to disable.")
#
# Add the ruby specific and protocol specific options
#
Ruby.define_options(parser)
args = parser.parse_args()
print("adding cpus (from routerless_synth_traffic.py)")
cpus = [ RouterlessSyntheticTraffic(
num_packets_max=args.num_packets_max,
single_sender=args.single_sender_id,
single_dest=args.single_dest_id,
sim_cycles=args.sim_cycles,
traffic_type=args.synthetic,
inj_rate=args.injectionrate,
precision=args.precision,
num_dest=args.num_dirs) \
for i in range(args.num_cpus) ]
print("defining the system (from routerless_synth_traffic.py)")
# create the desired simulated system
system = System(cpu = cpus, mem_ranges = [AddrRange(args.mem_size)])
print("set voltage domain (from routerless_synth_traffic.py)")
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = args.sys_voltage)
print("set system clock domain (from routerless_synth_traffic.py)")
system.clk_domain = SrcClockDomain(clock = args.sys_clock,
voltage_domain = system.voltage_domain)
print("creating routerless system (from routerless_synth_traffic.py)")
Ruby.create_routerless_system(args, False, system)
print("set ruby clock domain (from routerless_synth_traffic.py)")
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = args.ruby_clock,
voltage_domain = system.voltage_domain)
print("add system ruby cpu ports (from routerless_synth_traffic.py)")
i = 0
for ruby_port in system.ruby._cpu_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
cpus[i].test = ruby_port.in_ports
i += 1
# -----------------------
# run simulation
# -----------------------
print("defining simulation root (from routerless_synth_traffic.py)")
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ps')
print("instantiating configurations (from routerless_synth_traffic.py)")
# instantiate configuration
m5.instantiate()
print("waiting for the exit event (from routerless_synth_traffic.py)")
# simulate until program terminates
exit_event = m5.simulate(args.abs_max_tick)
print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# 2016 Georgia Institute of Technology
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.objects import *
from common import FileSystemConfig
from topologies.BaseRouterlessTopology import SimpleRouterlessTopology
# Creates a generic NoC assuming an equal number of cache
# and directory controllers.
class Routerless_XY(SimpleRouterlessTopology):
description='Routerless_XY'
def __init__(self, controllers):
self.nodes = controllers
def makeRouterlessTopology(self, options, network, IntLink, InjectionLink,
EjectionLink, RLInterface, Loop):
print("hello similu")
nodes = self.nodes # controllers
# getting num_cpus from the commandline (some options have default values)
num_rls = options.num_cpus # number of RLInterfaces and cpus are equal
num_rows = options.rl_rows # getting the number of rows from the commandline
num_eject_links = options.eject_links # getting the number of ejection links
# (***) loops should be generated automatically, not from a user's input.
# you can't say I want a 4x4 NoC with 1000 loops!
num_loops = 10 # (***) only for 4x4 NoC (modify later)
# default values for link latency and RLInterface latency.
# Can be over-ridden on a per link/RLInterface basis
link_latency = options.link_latency # used by simple, garnet and routerless
rl_latency = options.rl_latency # only used by routerless
# There must be an evenly divisible number of cntrls to RLInterfaces
# Also, obviously the number or rows must be <= the number of RLInterfaces
# The following divides the number of controllers by number of RLInterfaces
# to see if any controller remains (not evenly divisible)
cntrls_per_rl, remainder = divmod(len(nodes), num_rls)
assert(num_rows > 0 and num_rows <= num_rls)
# This is why we don't have rl_cols parameter.
# Number of columns is calculated automatically.
num_columns = int(num_rls / num_rows) # Ex: 16/4=4
assert(num_columns * num_rows == num_rls)
# create the loops for this routerless topology
# (***) this is the part for loop creation function
loops = [Loop(loop_id=i, direction = "clockwise") \
for i in range(num_loops)]
loops[1].direction = "anticlockwise"
loops[2].direction = "anticlockwise"
network.loops = loops # Add the loops to the network
# Create the RLInterfaces in the NoC (here all RLInterfaces have the same latency)
rls = [RLInterface(rl_id=i, latency = rl_latency) \
for i in range(num_rls)]
network.rls = rls # Add the created RLInterfaces to the network
# link counter to set unique link ids
link_count = 0
# Add all but the remainder nodes to the list of nodes to be uniformly
# distributed across the network. We're not adding the remaining cntrls
# to the network now. We add them as DMA controllers to RLInterface 0 later.
network_nodes = []
remainder_nodes = []
for node_index in range(len(nodes)):
if node_index < (len(nodes) - remainder):
network_nodes.append(nodes[node_index])
else:
remainder_nodes.append(nodes[node_index])
# Connect each node to the appropriate RLInterface (InjectionLinks & EjectionLinks)
# We have several level of cntrls (if number of cntrls > num_RLInterfaces)
injection_links = []
for (i, n) in enumerate(network_nodes):
# For each controller find its level, and id
# of the RLInterface to connect to.
cntrl_level, rl_id = divmod(i, num_rls)
assert(cntrl_level < cntrls_per_rl) # ex: 0,1,2<3
injection_links.append(InjectionLink(link_id=link_count, ext_node=n,
int_node=rls[rl_id],
latency = link_latency))
link_count += 1
# Connect the remainding nodes to RLInterface 0. These should only be
# DMA nodes.
for (i, node) in enumerate(remainder_nodes):
assert(node.type == 'DMA_Controller')
assert(i < remainder)
injection_links.append(InjectionLink(link_id=link_count, ext_node=node,
int_node=rls[0],
latency = link_latency))
link_count += 1
network.injection_links = injection_links # Add the injection links to the network
ejection_links = []
for (i, n) in enumerate(network_nodes):
# For each controller find its level, and id
# of the RLInterface to connect to.
cntrl_level, rl_id = divmod(i, num_rls)
assert(cntrl_level < cntrls_per_rl) # ex: 0,1,2<3
for _ in range(num_eject_links):
ejection_links.append(EjectionLink(link_id=link_count, ext_node=n,
int_node=rls[rl_id],
latency = link_latency))
link_count += 1
# Connect the remainding nodes to RLInterface 0. These should only be
# DMA nodes.
for (i, node) in enumerate(remainder_nodes):
assert(node.type == 'DMA_Controller')
assert(i < remainder)
for _ in range(num_eject_links):
ejection_links.append(EjectionLink(link_id=link_count, ext_node=node,
int_node=rls[0],
latency = link_latency))
link_count += 1
network.ejection_links = ejection_links # Add the ejection links to the network
# Create the routerless NoC IntLinks.
int_links = []
#==================================================================
# loop0 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[5],
dst_node=rls[6],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[0]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[6],
dst_node=rls[10],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[0]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[10],
dst_node=rls[9],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[0]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[9],
dst_node=rls[5],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[0]))
link_count += 1
#==================================================================
# loop1 (anticlockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[6],
dst_node=rls[5],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[1]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[5],
dst_node=rls[9],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[1]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[9],
dst_node=rls[10],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[1]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[10],
dst_node=rls[6],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[1]))
link_count += 1
#==================================================================
# loop2 (anticlockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[3],
dst_node=rls[2],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[2],
dst_node=rls[1],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[1],
dst_node=rls[0],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[0],
dst_node=rls[4],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[4],
dst_node=rls[8],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[8],
dst_node=rls[12],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[12],
dst_node=rls[13],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[13],
dst_node=rls[14],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[14],
dst_node=rls[15],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[15],
dst_node=rls[11],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[11],
dst_node=rls[7],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[7],
dst_node=rls[3],
src_port=0,
dst_port=0,
latency = link_latency,
loop=loops[2]))
link_count += 1
#==================================================================
# loop3 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[0],
dst_node=rls[1],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[1],
dst_node=rls[5],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[5],
dst_node=rls[9],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[9],
dst_node=rls[13],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[13],
dst_node=rls[12],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[12],
dst_node=rls[8],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[8],
dst_node=rls[4],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[4],
dst_node=rls[0],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[3]))
link_count += 1
#==================================================================
# loop4 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[0],
dst_node=rls[1],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[1],
dst_node=rls[2],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[2],
dst_node=rls[6],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[6],
dst_node=rls[10],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[10],
dst_node=rls[14],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[14],
dst_node=rls[13],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[13],
dst_node=rls[12],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[12],
dst_node=rls[8],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[8],
dst_node=rls[4],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[4],
dst_node=rls[0],
src_port=2,
dst_port=2,
latency = link_latency,
loop=loops[4]))
link_count += 1
#==================================================================
# loop5 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[1],
dst_node=rls[2],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[2],
dst_node=rls[3],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[3],
dst_node=rls[7],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[7],
dst_node=rls[11],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[11],
dst_node=rls[15],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[15],
dst_node=rls[14],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[14],
dst_node=rls[13],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[13],
dst_node=rls[9],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[9],
dst_node=rls[5],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[5],
dst_node=rls[1],
src_port=3,
dst_port=3,
latency = link_latency,
loop=loops[5]))
link_count += 1
#==================================================================
# loop6 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[2],
dst_node=rls[3],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[3],
dst_node=rls[7],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[7],
dst_node=rls[11],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[11],
dst_node=rls[15],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[15],
dst_node=rls[14],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[14],
dst_node=rls[10],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[10],
dst_node=rls[6],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[6],
dst_node=rls[2],
src_port=1,
dst_port=1,
latency = link_latency,
loop=loops[6]))
link_count += 1
#==================================================================
# loop7 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[0],
dst_node=rls[1],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[1],
dst_node=rls[2],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[2],
dst_node=rls[3],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[3],
dst_node=rls[7],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[7],
dst_node=rls[6],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[6],
dst_node=rls[5],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[5],
dst_node=rls[4],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[4],
dst_node=rls[0],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[7]))
link_count += 1
#==================================================================
# loop8 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[4],
dst_node=rls[5],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[5],
dst_node=rls[6],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[6],
dst_node=rls[7],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[7],
dst_node=rls[11],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[11],
dst_node=rls[10],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[10],
dst_node=rls[9],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[9],
dst_node=rls[8],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[8],
dst_node=rls[4],
src_port=5,
dst_port=5,
latency = link_latency,
loop=loops[8]))
link_count += 1
#==================================================================
# loop9 (clockwise)
int_links.append(IntLink(link_id=link_count,
src_node=rls[8],
dst_node=rls[9],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[9],
dst_node=rls[10],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[10],
dst_node=rls[11],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[11],
dst_node=rls[15],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[15],
dst_node=rls[14],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[14],
dst_node=rls[13],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[13],
dst_node=rls[12],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
int_links.append(IntLink(link_id=link_count,
src_node=rls[12],
dst_node=rls[8],
src_port=4,
dst_port=4,
latency = link_latency,
loop=loops[9]))
link_count += 1
network.int_links = int_links # Add the internal links to the network
#==================================================================
# Register nodes with filesystem
def registerTopology(self, options):
for i in range(options.num_cpus):
FileSystemConfig.register_node([i],
MemorySize(options.mem_size) // options.num_cpus, i)
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