Hello, I am trying something related to the global bit of a TLB entry and found that the gem5 code might have inconsistency with the Intel manual.
The Intel manual says that "a logical processor may use a global TLB entry to translate a linear address, even if the TLB entry is associated with a PCID different from the current PCID". However in TLB::translate(), gem5 concatenates the PCID to the vaddr when CR4.pcide is true and lookup the trie containing the TLB entries using [vaddr + PCID] without considering the global bits of the entries. Is the gem5 behavior a bug, or is it a subset of allowed behaviors? I guess it depends on what the word "may" in the manual means, but not quite sure. Best regards, Soramichi Akiyama _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
