[gem5-users] Simulation memory Object with Atomic Requests and Responses

[Abdlerhman Abotaleb]

Hello All, I'm trying to implement a simulation memory object that accepts atomic requests on its CPUSide port (response port) and forwards them to the memory controller. This simulation object is connected to cache from the CPUSidePort and to Memory controller from memSidePort. It works fine with timing requests and responses. For Atomic requests, I override the recvAtomic making it calls sendAtomic in the Request port          Inside the CPUSidePort(which is defined inside the simulation object scope , inherit from ResponsePort) :          Tick recvAtomic(PacketPtr pkt) override           {                           owner->handleAtomic(pkt);           // handleAtomic  defined in the simulation object           }         &  Inside the Simulation object:          void          simulationMemObect::handleAtomic(PacketPtr pkt)          {              memSidePort.sendAtomic(pkt);         } I don't know how to implement the response receive handling , there's no function to override called recAtomicResp , similar to recvTimingResp in TimingRequestProtocol (One of RequestPort class parents). For now, If run GEM5 , it ends with core dump at the beginning with the following output when try to debug with GDB: received signal SIGILL, Illegal instruction. 0x000000000117bdf1 in gem5:: simulationMemObect ::CPUSidePort::recvAtomic(gem5::Packet*)

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