Hi Ziyang, Based on my understanding, in SE mode, you can get both cores to execute the same binary but they will run using different addresses because they are two processes and have their own address space. If you want to test cache coherence, you might want to run a multi-threaded program that has shared data accessed by different threads mapped to different cores.
Best, Jiayi On Thu, Jun 16, 2022 at 4:23 PM Peng, Ziyang <ziyang.p...@intel.com> wrote: > Hi everyone, > > I’m trying to run same workload by multi cores in SE mode in order to test > some cache coherence issues. (Using risc-v core) > > For example, I add a process to cpu[0] by using “*system.cpu[0].workload > = process*”. It works, cpu[0] will run the workload correctly in the > simulation. Then I try to add this process to cpu[1] by using > “*system.cpu[1].workload > = process*”. In simulation, only cpu[0] will run the workload. By > checking generated config file, cpu[1] do not have its own workload. It > will sleep whole time in the simulation. This is reasonable. So I try to > create 2 processes(Using same binary) and bind them to 2 cores. In this > time, both core will run its own workload correctly. This is because they > loaded executables separately and accessed from different memory addresses > which will not cause any cache coherence issues like read shared in their > L1 cache. After checking code, I found that address transfer will happened > in MMUTranslationGen(). For different processes, each memory allocation is > independent. > > Here is my question: > > 1. Is there any way to let both core execute same binary in same > memory address in SE mode? > 2. Can I let a core run same binary serval times in one simulation? > 3. Is there any tools to test cache coherence protocol in gem5 ? > > > > Thanks + regards, > > Ziyang > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org >
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