Thank you for the reply Tom.

In my case, I have been able to fix it by supplying the
"decoder=ArchDecoder()" parameter to the cpu_class constructor when
switch_cpus is first initialized. (Line 465 in Simulation.py)

> switch_cpus = [cpu_class(switched_out=True, cpu_id=(i),
decoder=ArchDecoder()) for i in range(np)]

- Gagan


On Mon, Jun 13, 2022 at 3:43 AM Tom Rollet <tom.rol...@huawei.com> wrote:

> Hello,
>
>
>
> I had the same problem when using kvm/o3 with repeat switch.
>
>
>
> I added a hacky fix in Simulation.py file where I assign the testsys
> decoder to the other cpu that does not have the decoder:
>
> Repeat_switch_cpus[0].decoder = testsys.cpu[0].decoder
>
>
>
> This seems to solve the issue. But I did not look more into detail what is
> the underlying problem.
>
>
>
> Tom
>
>
>
> *From:* Gagan Panwar <gaganpan...@gmail.com>
> *Sent:* 13 June 2022 08:06
> *To:* gem5-users@gem5.org
> *Subject:* [gem5-users] Gem5 segfaults in build/X86/cpu/o3/fetch.cc
>
>
>
> Hi everyone,
>
> I'm trying to run the latest version of Gem5 under X86 and it segfaults at
> the following line:
>
>
>
> build/X86/cpu/o3/fetch.cc:139
> > decoder[tid] = params.decoder[tid];
>
>
>
> gdb says params.decoder is a "vector of length 0". Looks like it has not
> been initialized.
>
> Any idea how to correctly initialize this?
>
>
>
> Here is my command line:
>
>
> ./build/X86/gem5.opt -r -d sim_output/stride/benchmark
> configs/example/fs.py --mem-size=16GB -n 4 -r 1
> --disk-image=/hdd0/newCPTs/ubuntu-server-16.04.6.img
> --checkpoint-dir=/hdd0/newCPTs/bench_1 --cpu-type=DerivO3CPU
> --rel-max-tick=2000000000 --l2-hwp-type=StridePrefetcher --caches --l2cache
> --kernel=vmlinux-5.4.49
>
> I have also tried assigning decoder[tid] to a new TheISA::Decoder() object
> in fetch.cc like it used to be in older versions but this leads to build
> issues.
>
> To reiterate, I have not modified a single line of code. I was able to
> take checkpoints under KVM mode successfully, however.
>
>
>
> Thank you,
>
> Gagan
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