Hi Giacomo, Thanks for the reply.
I’m looking to replay both compute instruction delays as well as memory system activity. Essentially have some sort of “X delay” per type of instruction (or some scaled CPI) and then have the memory commands execute as well. Ideally, we’d actually something similar to a cycle accurate model that: 1. Models the real pipeline delay of instructions 2. Recognizes dependencies such that memory operations can correctly stall compute instructions in the trace This is probably not supported by TraceCPU currently I imagine. It’s some hybrid of O3CPU and TraceCPU. From: Giacomo Travaglini <giacomo.travagl...@arm.com> Date: Monday, April 25, 2022 at 6:27 AM To: gem5-users@gem5.org <gem5-users@gem5.org> Cc: Jonathan Kang <mos...@fb.com> Subject: Re: TraceCPU and ARM ETM Hi Jonathan, thanks for your email. I haven't heard of anything like that, but it would be really nice to have an ETM trace player available in gem5. Have you had a look at the TraceCPU documentation available in the gem5 website? [1] The TraceCPU is really supposed to be used for memory-system design explorations, abstracting away the core microarchitecture. Is this what you are looking for? Are you just interested on injecting instruction/data packets, or do you want your trace player to parse and act on a richer set of information? If that is the case, doing an off-line translation from ETM format to elastic trace format might not be what you are looking for. What you could do is to *re-use* part of the TraceCPU code (basically the back-end packet generation) and write your own front-end (ETM parser) and middle logic. Let me know what you think about it. Kind regards, Giacomo ________________________________ From: Jonathan Kang via gem5-users <gem5-users@gem5.org> Sent: 13 April 2022 22:17 To: gem5-users@gem5.org <gem5-users@gem5.org> Cc: Jonathan Kang <mos...@fb.com> Subject: [gem5-users] TraceCPU and ARM ETM Hi all, I’m new to Gem5 (just Googled it) and am interested in TraceCPU. A bit of background on what I’m trying to achieve: 1. I have a device (Snapdragon) that I am capturing ARM ETM traces on. 2. I’m looking for a way to use a trace-driven CPU model to replay these ARM traces in my performance model. 3. Unfortunately, the models from ARM do not support trace-driven; they’re execution-driven only. I’ve read that TraceCPU does consume a trace but that it only supports traces that are generated by O3CPU (with certain timing annotations). I was wondering: has anyone tried converting ETM (possibly with timestamps?) into a format that TraceCPU can consume? Second question: is there documentation that describes the TraceCPU trace format? Perhaps I can write such a tool that’s (decently) accurate. Thanks in advance for any advice! Jonathan. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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