Hello,
I would like to simulate the system by using gem5 and DRAMsim3.
I downloaded and compiled successfully a gem5+DRAMsim3 integration from
https://github.com/umd-memsys/gem5.
However, I cannot boot the system in full system simulation
with TimingSimpleCPU model. This is the error that I encountered:
gem5.opt: build/X86/mem/dramsim3.cc:226: bool
DRAMsim3::recvTimingReq(PacketPtr): Assertion
`wrapper.canAccept(pkt->getAddr(), pkt->isWrite())' failed.
This is a command that i used to run X86 full system simulation:
./build/X86/gem5.opt --debug-flag=DRAMsim3 --debug-file=debug.txt \
./configs/example/fs.py --kernel=x86_64-vmlinux-4.9.92 \
--num-cpu=1 --cpu-clock=4.4GHz --caches --l2cache
--cpu-type=AtomicSimpleCPU \
--mem-type='DRAMsim3'
--dramsim3-ini="ext/dramsim3/DRAMsim3/configs/DDR4_4Gb_x4_2133.ini" \
--disk-image=x86root.img \
--root-device=/dev/sda1
Could you help me with this?
Thank you in advance!
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