Hi Becker:
Thank for your reply.
When I modify the code like yours, some error when I compile:
scons: Building targets ...
[ISA DESC] ARM/arch/arm/isa/main.isa -> generated/decoder-g.cc.inc,
generated/decoder-ns.cc.inc, generated/decode-method.cc.inc,
generated/decoder.hh, generated/decoder-g.hh.inc, generated/decoder-ns.hh.inc,
generated/exec-g.cc.inc, generated/exec-ns.cc.inc, generated/decoder.cc,
generated/inst-constrs-1.cc, generated/inst-constrs-2.cc,
generated/inst-constrs-3.cc, generated/generic_cpu_exec_1.cc,
generated/generic_cpu_exec_2.cc, generated/generic_cpu_exec_3.cc,
generated/generic_cpu_exec_4.cc, generated/generic_cpu_exec_5.cc,
generated/generic_cpu_exec_6.cc
[ CXX] ARM/mem/ruby/protocol/Cache_Controller.cc -> .o
[ CXX] ARM/mem/ruby/protocol/Cache_Wakeup.cc -> .o
[VER TAGS] -> ARM/sim/tags.cc
[ CXX] ARM/sim/tags.cc -> .o
[ CXX] ARM/arch/arm/generated/inst-constrs-3.cc -> .o
[ CXX] ARM/arch/arm/generated/inst-constrs-1.cc -> .o
[ CXX] ARM/arch/arm/generated/inst-constrs-2.cc -> .o
In file included from build/ARM/arch/arm/generated/inst-constrs-3.cc:9:
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr
ArmISAInst::Aarch64::decodeBranchExcSys(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:90482:12: error: could not
convert 'ArmISAInst::NopInst(machInst)' from 'ArmISAInst::NopInst' to
'StaticInstPtr' {aka 'RefCountingPtr<StaticInst>'}
90482 | return NopInst(machInst);
| ^~~~~~~~~~~~~~~~~
| |
| ArmISAInst::NopInst
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr
ArmISAInst::Aarch64::decodeSmeContigLoadSS(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:99981:26: warning: unused
variable 'imm' [-Wunused-variable]
99981 | uint64_t imm = (uint64_t) bits(machInst, 3, 0);
| ^~~
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr
ArmISAInst::Aarch64::decodeSmeContigStoreSS(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:100042:26: warning: unused
variable 'imm' [-Wunused-variable]
100042 | uint64_t imm = (uint64_t) bits(machInst, 3, 0);
| ^~~
scons: *** [build/ARM/arch/arm/generated/inst-constrs-3.o] Error 1
-----邮件原件-----
发件人: Pedro Becker via gem5-users [mailto:gem5-users@gem5.org]
发送时间: 2022年1月25日 18:16
收件人: gem5-users@gem5.org
抄送: Pedro Becker <pe...@ac.upc.edu>
主题: [gem5-users] Re: restore with O3 hang when "bti" instrution meet
Hi Liyuchao,
I'm assuming you are referring to ARM ISA...
BTI is appearing on your code but it's not implemented.
"A BTI instruction is used to guard against the execution of instructions that
are not the intended target of a branch. Outside of a guarded memory region, a
BTI instruction executes as a NOP. "
(See here:
https://developer.arm.com/documentation/100076/0100/a64-instruction-set-reference/a64-general-instructions/bti)
My understanding is that if you are not trying to investigate how this guarding
mechanism works (say, because you are investigating hardware security or
whatever), you can simply ignore that instruction as if your code is outside of
a guarded memory region.
So in src/arch/arm/isa/formats/aarch64.isa you can find the bti instruction and
return a NOP instead of an unimplemented instruction. Something like this:
- return new WarnUnimplemented("bti", machInst);
+ return new NopInst(machInst);
Recompile gem5 and check if it does the trick.
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