Hi Gabe, Thank you for your response. We understand that the execution environments in gem5's SE mode and on a real system differ and we aren't expecting identical behavior, e.g., the same addresses, etc. However, the problem here appears to be an inconsistency in the simulated state itself, the value of the target register and the source memory differ after the load instruction (please see the end of my original message).
How would you explain that? Thanks, Balazs _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
