Hi Jason. Some instructions need to be broken down into microops because they might not be realistic to do all at once, or because they need to perform multiple memory accesses. Other instructions don't, so they're implemented as regular instructions which are not broken down into microops.
Gabe On Wed, Dec 8, 2021 at 4:22 PM Jason Z via gem5-users <gem5-users@gem5.org> wrote: > Hello Everyone, > > I hope you are all doing well! > > I am trying to implement a store instruction in ARM that has Post-index, > Pre-index, and Signed-offset versions, and I'm using a normal store (i.e., > STRX64) as a model to start, but I am running into some confusion with > regard to which versions are microops, macroops, and neither, so I was > wondering if anyone had any clarification on the issue > > I am seeing information about the differences in X86, but I haven't been > able to find anything about it in ARM > > Here is what I've gathered so far: > > STRX64_REG → neither (not IsMicroop/IsMacroop) > STRX64_PRE → IsMacroop (uses microop MicroAddXiUop) > STRX64_POST → IsMacroop (uses microop MicroAddXiUop) > STRX64_IMM → neither (not IsMicroop/IsMacroop) > STRX64_PREAcc → IsMicroop > STRX64_POSTAcc → IsMicroop > > From my understanding, the macroop is broken down into microops, but I am > confused as to why some of the others are listed as microops and some are > listed as neither. If anyone has any insight into how these are different > and how they are used, it would be greatly appreciated > > Thank you for your time! > > Respectfully, > > Jason Z > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
