Hello Giacomo, Thanks for your reply. I understand what you mean is that if I rename fp operations, it will need to rename the single/double precision operand, and in gem5 we use elements of SIMD vector registers to do this kind of rename. But I still get confused why we use the elements of SIMD registers rather than float registers to do this.
In configs/common/cores/arm/03_ARM_v7a.py, I saw we set the number of physical float registers to be 192. Using rename debug-flag, it seems that we didn't use physical float registers during the fp operations. Because in my opinion, in ARM ISA, only we use neon/sve extension, the instruction will have vector register identifier and it can notice the processor we need the vector registers to do vector operations. Thanks, Gelin _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
