This is a complex question. CHI is an ARM protocol which obviously work for ARM ISA's... At least. Does it work for x86? There are good chances that the answer is "yes" because x86 memory model is more restrictive than ARM's. If you need an assertive answer though, I can't give it to you. This is tricky as the ISA memory model will interfere with the cache coherence protocol properties. You might be in trouble when running apps that make use of atomic instructions and memory fences. If you are familiar with memory consistency/coherency issues, you know waht I mean. If not, this is a good start to answer such question ;)
And if anyone has a guess on that... thanks in advance ;) Gabriel _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
