Hi again,
just wanted to give this a second try. No urgent matter here, just some
lack of understanding and curiosity on my side.
Thank you,
Vincent
Am 04.06.2021 um 11:34 schrieb Vincent R.:
Hi everyone,
I am currently doing some experiments with packet timings in the
Memory Controller( gem5 version 20.1.0.2., SE mode). As I understood
it, writes accesses are serviced instantly by the controller and their
actual timing is only calculated later when the corresponding
nextReqEvent is processed and the packet is removed from the write queue.
This works fine, however, with default parameters set, there are still
a lot of write packets left in the queue, when the simulation exits.
So, in my understanding, these are never correctly timed.
As I was experimenting I set the write threshold parameters of MemCtrl
in a way to force the controller to process all writes. Naturally the
run time increases by a large amount of ticks.
My question: How does gem5 perform a correct timing simulation while
leaving untimed writes in the queue at the end of simulation? Or
doesn't it? Have I misunderstood something?
Test system is a simple example configuration without caches.
Thank you for your help.
Vincent
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