Hi, all -- I've been using an older version of Gem5 for some time (inherited from an existing project) for some ARM simulations, but now am moving to do something new on x86.
The particular task where I'd like some guidance is this: I want to add an instruction that will send a command to the cache(s). It does not need to mention a specific address, but may send some data. I was thinking of encoding it the same way as clwb, but using the currently disallowed 11 (i.e., 3) combination of the mod/rm bits. This generally indicates a register as opposed to a memory operand. I think I have found more or less where to do this in the decoder, but if someone would respond about that, it would be helpful. Then there is the question of the other steps of adding an instruction, which starts getting more mysterious (e.g., what does Iz, for example mean, and is it what I want if I want this new instruction to have a register operand?). It will seem I'll need to add a micro-op as well. I can follow the clwb model for that, except that this special thing will probably use some new flag in its request/packet that will head toward the cache (and of course I will be extending the cache to notice and handle that for the new thing I'm devising). An overall sketch of how to accomplish this successfully and going with the flow of the design would be great. If there are specific pieces of documentation I should be looking at it, pointers to them would also be gratefully accepted. Regards, and thanks in advance - Eliot Moss _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
