Hello everyone, I believe I found a small problem with the way custom timings
are handled through the MinorFUTiming class. I wanted to submit it to the
tracker but the Jira webpage constantly keeps refreshing and I can't access any
issue pages. If anybody knows an alternate way to make this issue known please
let me know.
I was trying to add a new functional unit to the MinorCPU through the python
interface and I specified some custom timings for a set of custom instructions
that I have. One snippet looked like this:
timings =
[MinorFUTiming(match=0x200300b,mask=0xfe00707f,description='shatransform',extraCommitLat=65,srcRegsRelativeLats=[0]),
MinorFUTiming(match=0x8000100b,mask=0xfe00707f,description='sipcompress',extraCommitLat=3,srcRegsRelativeLats=[0]),
MinorFUTiming(match=0x8000200b,mask=0xfe00707f,description='sipfinalize',extraCommitLat=4,srcRegsRelativeLats=[0])]
But I noticed the extraCommitLat values were not affecting anything in my
simulations. I tracked the issue down to a function called findTiming in
/gem5/src/cpu/minor/func_unit.cc . It seems this is the function responsible
for finding this extra timing information. However, there is a conditional
directive at the beginning of the function that is as follows:
#if THE_ISA == ARM_ISA
/* This should work for any ISA with a POD mach_inst */
TheISA::ExtMachInst mach_inst = inst->machInst;
#else
/* Just allow extra decode based on op classes */
uint64_t mach_inst = 0;
#endif
So if gem5 is not built for ARM, it seems you can only specify extra timing
information for op classes in general. Different instructions from the same op
class will not get assigned timing information even if you specify it as I did
above. I changed the conditional to be (THE_ISA == ARM_ISA) || (THE_ISA ==
RISCV_ISA) , and that seems to have fixed the issue.
If anybody working with RISC-V builds experienced similar issues maybe this can
help. Also let me know if this fix is somehow not appropriate or might have
other consequences to be mindful of.
Thanks.
PS: As an off-topic question, does anyone know of a reliable way to instrument
code running in SE mode for RISC-V? I asked a similar question here before,
m5ops was suggested but there are no m5ops pseudo-instructions implemented for
RISC-V as of now to the best of my knowledge. I've been trying to make use of
hardware performance counters (for instance using rdcycle), but I find that its
unreliable and doesn't add up when compared to the stat dump that I see from
gem5. Thanks in advance.
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