Hello all,
I am trying to create a system having multiple CPUs by passing a list of
CPU to the system.cpu. So far it works with TimingSimpleCPU, but for the
DerivO3CPU it crashes. I include the crash log, the python config file, and
the C workload file. I am using gem5 20.1, pulled from the stable
branch, gcc version 7.5.0 (Ubuntu 7.5.0-3ubuntu1~18.04), python 2.7.17. The
command line I use is:
./build/X86/gem5.opt configs/tutorial/two_core.py
The 2 binary files for 2 workloads are almost the same, I just change the
text in printf, and the number of loops.
I also wonder that by passing a list of CPU to the system.cpu, am I
creating a system is 1 multicore CPU or a system with multiple separate
CPU? And how to pass multiple workloads on 1 CPU? I saw it accept a list,
but it throws an error if I pass a list with more than 1 workload.
Best regards,
Duc Anh
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version 20.1.0.0
gem5 compiled Nov 5 2020 18:11:27
gem5 started Nov 9 2020 09:57:07
gem5 executing on Dauto98-ROG-Strix-G531GD, pid 10493
command line: ./build/X86/gem5.opt configs/tutorial/two_core.py
warn: l2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: l2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: interrupts.int_master is deprecated. `int_master` is now called
`int_requestor`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: interrupts.int_slave is deprecated. `int_slave` is now called
`int_responder`
warn: l2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: l2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: interrupts.int_master is deprecated. `int_master` is now called
`int_requestor`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: interrupts.int_slave is deprecated. `int_slave` is now called
`int_responder`
warn: l2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and
pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7001
Beginning simulation
info: Entering event queue @ 0. Starting simulation...
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall access(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
warn: ignoring syscall mprotect(...)
Looping goodbye, 0 time
Looping hello, 0 time
Looping hello, 1 time
Looping goodbye, 1 time
Looping hello, 2 time
Looping goodbye, 2 time
Looping hello, 3 time
Looping goodbye, 3 time
Looping hello, 4 time
Looping goodbye, 4 time
Looping hello, 5 time
Looping goodbye, 5 time
Looping hello, 6 time
Looping goodbye, 6 time
Looping hello, 7 time
Looping goodbye, 7 time
Looping goodbye, 8 time
Looping goodbye, 9 time
hello world
Goodbye world
gem5.opt: build/X86/cpu/o3/cpu.cc:823: void
FullO3CPU<Impl>::removeThread(ThreadID) [with Impl = O3CPUImpl; ThreadID =
short int]: Assertion `commit.rob->isEmpty(tid)' failed.
Program aborted at tick 322773000
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x55a6c77d158c]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x55a6c77e40aa]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x128a0)[0x7f31e43db8a0]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f31e29b7f47]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f31e29b98b1]
/lib/x86_64-linux-gnu/libc.so.6(+0x3042a)[0x7f31e29a942a]
/lib/x86_64-linux-gnu/libc.so.6(+0x304a2)[0x7f31e29a94a2]
./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE12removeThreadEs+0x194)[0x55a6c79ef664]
./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE11haltContextEs+0x64)[0x55a6c79ef994]
./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE11exitThreadsEv+0x8d)[0x55a6c79f05ad]
./build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xa5)[0x55a6c77d9a65]
./build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x87)[0x55a6c77feb27]
./build/X86/gem5.opt(_Z8simulatem+0xcba)[0x55a6c77ffb7a]
./build/X86/gem5.opt(+0xb5db61)[0x55a6c7bfbb61]
./build/X86/gem5.opt(+0x6ac8b9)[0x55a6c774a8b9]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyCFunction_Call+0x96)[0x7f31e47fb736]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x76e0)[0x7f31e476cb20]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f31e4763a0f]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f31e47640fc]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f31e476a303]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f31e4763a0f]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f31e47644ce]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCode+0x1b)[0x7f31e476524b]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x18855d)[0x7f31e477055d]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyCFunction_FastCallDict+0x1bb)[0x7f31e47fb53b]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c1ec)[0x7f31e47641ec]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f31e476a303]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f31e4763a0f]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f31e47640fc]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f31e476a303]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f31e4763a0f]
/usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f31e47644ce]
--- END LIBC BACKTRACE ---
Aborted (core dumped)
from collections import namedtuple
import m5
from m5.objects import *
from caches import *
option = namedtuple('option', ('l1i_size', 'l1d_size', 'l2_size'))('128MB', '128MB', '512MB')
def createCPU(l2bus, membus):
# create the CPU
cpu = DerivO3CPU()
# create L1 cache
cpu.icache = L1ICache(option)
cpu.dcache = L1DCache(option)
cpu.icache.connectCPU(cpu)
cpu.dcache.connectCPU(cpu)
# connect to shared cache level 2 bus
cpu.icache.connectBus(l2bus)
cpu.dcache.connectBus(l2bus)
# create and connect interrupt port
cpu.createInterruptController()
cpu.interrupts[0].pio = membus.master
cpu.interrupts[0].int_master = membus.slave
cpu.interrupts[0].int_slave = membus.master
return cpu
# The System object, root of all other component
system = System()
# set up the clock and the voltage
# It seems like the frequency is the same for all cpu
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# setup memory simulation
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
# create L2 bus
system.l2bus = L2XBar()
# create the system wide bus
system.membus = SystemXBar()
# create 2 cpus
system.cpu = [createCPU(system.l2bus, system.membus), createCPU(system.l2bus, system.membus)]
# create L2 Cache
system.l2cache = L2Cache(option)
system.l2cache.connectCPUSideBus(system.l2bus)
system.l2cache.connectMemSideBus(system.membus)
system.system_port = system.membus.slave
# create memory controller
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
# create the process workload for the cpu
process1 = Process(pid = 100)
process1.cmd = ['tests/test-progs/hello/bin/hello']
# the fact that workload accepting an array indicate that a cpu can handle multiple command
system.cpu[0].workload = [process1]
system.cpu[0].createThreads()
# create the process workload for the cpu
process2 = Process(pid = 200)
process2.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
# the fact that workload accepting an array indicate that a cpu can handle multiple command
system.cpu[1].workload = [process2]
system.cpu[1].createThreads()
# create the root and start the system
root = Root(full_system = False, system = system)
m5.instantiate()
print("Beginning simulation")
exit_event = m5.simulate()
print('Exiting @ tick {} because {}'.format(m5.curTick(), exit_event.getCause()))/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
int main(int argc, char* argv[])
{
for (size_t i = 0; i < 8; i++) {
printf("Looping hello, %zu time\n", i);
}
printf("hello world\n");
return 0;
}
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