Hi all, Haven't heard anything from anyone. It would really be appreciated if someone can provide any comment/suggestion/clarification on this.
Thanks, Aritra On Tue, 15 Sep, 2020, 3:41 PM Aritra Bagchi, <bagchi95ari...@gmail.com> wrote: > Hi all, > > I have two questions regarding the classic cache of gem5. They are as > follows: > > 1. Last-level caches in real hardware are usually not monolithic but are > multi-banked. It seems multiple banking can be efficient only if the memory > accesses are spread uniformly across all banks. Can such banking be > implemented in gem5 classic cache? Could someone provide any hint on how to > do that? > > 2. I have experimented with gem5 caches and found that a memory request > which is a miss at the last-level cache (L3) has to traverse the entire > memory hierarchy: L1-D (miss) > L2 (miss) > L3 (miss) > main memory (fetch > data) > L3 (miss-fill/write) > L2 (miss-fill/write) > L1-D > (miss-fill/write) . When the response comes from the main memory, I want to > bypass it to the L2 cache and let the miss-fill happen independently at L3 > taking whatever latency it should take for an L3 write operation. I wanted > to make sure that the requesting core does not have to stall (wait) for the > miss-fill to finish, and can get the data as soon as it becomes available > from the main memory. Could someone put some light on how can this be > implemented in gem5? > > Any comment/suggestion/clarification will be highly appreciated. > > Thanks and regards, > Aritra >
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