It's a regular inorder 5 stage pipeline model designed to mimic the microarchitectural states of actual C-class processor mentioned here. https://gitlab.com/shaktiproject/cores/c-class
Has fetch, decode(modified), execute, memaccess, writeback connected through pipe like structures containing FIFOs, with operand forward. Working on BPU and Fault handling. Currently tested only with RISCV ISA in baremetal full system simulation. The model can be found here : https://gitlab.com/shaktiproject/tools/core-models-gem5 On Fri, 3 Jul, 2020, 4:07 AM Anuj Falcon, <anujfalc...@gmail.com> wrote: > How to know if my CPU model qualifies to be upstreamed with the rest of > the CPU models in gem 5 ? >
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