Thanks Ayaz, I am noticing that other ISAs have this file but X86 doesnt
have it

./arch/alpha/isa/branch.isa
./arch/arm/isa/formats/branch.isa
./arch/arm/isa/insts/branch.isa
./arch/arm/isa/templates/branch.isa
./arch/mips/isa/formats/branch.isa
./arch/power/isa/formats/branch.isa
./arch/sparc/isa/formats/branch.isa

For example, in the cpu/pred/bpred_unit.cc, when I print the following

inst->isDirectCtrl() or inst->isIndirectCtrl()

both flag are not set for any instruction

Thanks
Niranjan


On Sat, Feb 15, 2020 at 1:56 AM Ayaz Akram <yazak...@ucdavis.edu> wrote:

> Hi Niranjan,
>
> Can you give some specific examples of instructions where you find these
> problems (and what cpu model are you using)? Is this issue on gem5 Jira (
> https://gem5.atlassian.net/projects/GEM5/issues/GEM5-338?filter=allopenissues&orderby=priority%20DESC)
> related to branch operation type behavior that you are seeing?
>
> Thanks
>
>
> On Fri, Feb 14, 2020 at 4:21 AM niranjan soundararajan <
> niranja...@gmail.com> wrote:
>
>> Hello
>>
>> How is the x64 support on Gem5. I am finding that the decoded
>> instructions don’t have their types set, for example branch instructions.
>> Has someone been able to resolve this issue
>>
>> Thanks
>> Niranjan
>> _______________________________________________
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> _______________________________________________
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to