Hi, if anyone has any details on cores a53 or a57 or a72 with respect to
their PRF (int and floating point) it would be of great help.

On Fri, Mar 1, 2019 at 9:16 AM, siva sankar <sankar.siva...@gmail.com>
wrote:

> Hi Ciro,
>
> Thank you for the quick response. I think  I wasn't clear on my question.
> What I was asking is basically the parameters required for modelling an
> ARM cortex a76 in gem5. I think you answered the question.
> I modified the ex5_big.py file in configs/common/cores/arm/ location with
> few parameters i found in
> https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse
> .
> Please tell me if this approach is good enough for modelling an ARM cortex
> a76 in gem5?
>
> ᐧ
>
> On Fri, Mar 1, 2019 at 1:21 AM Ciro Santilli <ciro.santi...@arm.com>
> wrote:
>
>> On 3/1/19 12:31 AM, siva sankar wrote:
>> > Hi all,
>> >
>> > Can someone help me or direct me on how to configure the ARM cortex a76
>> > in gem5?
>> >
>>
>> What do you mean more precisely? I can't find any references to A76
>> in-tree.
>>
>> For the ISA interface purely, we have very few "enable this feature"
>> flags in the config, for the most part it is mostly on an "enable
>> everything that is implemented by default" basis.
>>
>> For performance modeling, I believe not enough public information is
>> made available for accurate modeling, have a look at
>> https://en.wikipedia.org/wiki/ARM_Cortex-A76 for some very high level
>> public known parameters you could try to replicate with custom configs
>> such as out-of-order or cache sizes.
>>
>> > Thanks
>> > --
>> > Thanks and regards
>> > Siva Sankar G
>> >
>> > _______________________________________________
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>> > gem5-users@gem5.org
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>> >
>>
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>
>
> --
> Thanks and regards
> Siva Sankar G
>
-- 
Thanks and regards
Siva Sankar G
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