Another reference is https://github.com/harvard-acc/gem5-aladdin
B.R /T From: gem5-users [mailto:[email protected]] On Behalf Of Andreas Brokalakis Sent: Friday, April 20, 2018 2:39 AM To: gem5 users mailing list <[email protected]> Cc: Tampouratzis Nikolaos <[email protected]> Subject: Re: [gem5-users] Connect CPU and accelerator through a bus Hi Jeckson, if you check the presentations from the latest gem5 workshop, in our group we have most probably already implemented what you are looking to do. Please check here: http://gem5.org/wiki/images/5/52/Summit2017_complex_fs_incorporating_accelerators.pdf If you think that this works for what you want to do, you may contact my colleague Nikos (cc'ed in this email). I am not sure if this work has been made available through github, but I am pretty sure a collaboration can be established anyway. Best, Andreas On Thu, Apr 19, 2018 at 7:15 PM, Jeckson Souza <[email protected] <mailto:[email protected]> > wrote: Hi Jason, Thanks for the reply and the code example! As a workaround, I was using a direct connection between multiple cores and one accelerator with a vector of ports, but I will definitely change to your approach. Cheers, Jeckson Dellagostin Souza PhD Student Instituto de Informática Universidade Federal do Rio Grande do Sul 2018-04-19 12:22 GMT-03:00 Jason Lowe-Power <[email protected] <mailto:[email protected]> >: Hi Jeckson, [Note: Just found this in my drafts. Sorry for the slow reply.] You could use memory-mapped I/O regions by using it as a PIODevice. Essentially, you can set up your accelerator to only respond to certain physical addresses by implementing getAddrRanges() to return just those addresses. Then, the CPU could read/write those addresses and communicate with your accelerator. This is similar to how devices work in real life. Memory-mapped I/O is simple to set up in SE mode. However, in FS mode it's more complicated since you actually have to write a kernel driver. Here's an example accelerator like you described: https://github.com/powerjg/gem5/tree/devel/accel/src/accel. That branch (devel/accel) has all of the necessary code. Cheers, Jason ----------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall https://faculty.engineering.ucdavis.edu/lowepower/ On Wed, Apr 4, 2018 at 8:30 AM Jeckson Souza <[email protected] <mailto:[email protected]> > wrote: Hi all, I'm trying to send instructions from a CPU to an accelerator through a SystemXBar (I need the bus as, eventually, I'll add more of these components to the system). In my first attempt, I tried to create ports on the CPU/accelerator similar to the ones used as memory ports so I could use the existing xbar to communicate. However, these Master/SlavePorts require me to use Packets and Requests, which, if I understand correctly, are tied to valid memory addresses. Does anybody know if there is an implemented bus/port type which I could use in this case? Regards, Jeckson _______________________________________________ gem5-users mailing list [email protected] <mailto:[email protected]> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] <mailto:[email protected]> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] <mailto:[email protected]> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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