Hi, I am trying to access a bit in tag of L1 cache line from a macro in the application. The implemented macro will get an address and will set the bit in the tag of related cache line.
For this, I implemented several functions in different classes such as: getRubyPtr in cpu/base.cc which returns a pointer to RubySystem object. getCacheCtrl in RubySystem which returns m_abs_cntrl_vec in RubySytem. Using the following line, I have the access to CacheControllers and therefore L1Cache_Controller (with doing iteration over the controllers). m_abs_cntrl_vec = tc->getCpuPtr()->getRubyPtr()->getCacheCtrl(); However, when I call L1Cache_Controller->getAccessPermission(line_address); I notice that the cache line is not present in tbe or L1 cache. (line_address is calculated using this function : line_address = makeLineAddress(address); and address is the address I have passed through macro.) Can you help me to figure it out why the address is not present in L1 cache? Is it possible because of address translation? Or am I missing an step? Thanks in advance. Best, Amin
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