Jason, Thank you very much for answering my question. I read some source code of /gem5/src/mem. As far as I read is about snoop protocal to keep different cpu's cache's consistency.
I know the shared memory is a place where cpus could exchange data, but what if I want cpu A to monitor cpu B and when meets condition the cpu A sends a signal and the cpu B would read data from shared memory. Does Gem5 have such a signal channel like signal bus where one cpu send signal to other cpu? Thanks! Qingran Wang > Hi Qingran, > > gem5 models the entire system including caches and the memory hierarchy. > Most communication between cores occurs through the memory hierarchy. So > you can simply modify the program to communicate via shared memory. If you > want to implement some new communication hardware between CPUs, I would > start by looking at the CPU code in src/cpu and go from there. > > Jason > > On Fri, Feb 17, 2017 at 8:01 AM magic王 <[email protected]> wrote: > > Hi everyone ! > > I am going to simulate two ARM cores in gem5 . And I have to achieve > some intercommunication between two cores so I should do some modification > in gem5's source code. But I can't find the place where gem5 simulates > multi-cores's intercommunication via shared memory or something else . Can > anyone help me with where gem5's cpu's intercommunication is ? > Or I can use SMT to simulate the dual-core architecture . But could > I modify the thread's intercommunication in cpu models with SMT such as o3 > cpu ? > > Thanks! > > > > Qingran Wang > _________________________________
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