Hello everyone，
Thanks for your advice. Now I'm trying to build a racetrack cache models by
myself. First of all，I want to creat a new SimObject same as "BaseCache" , then
I can chang it as I wish. I have create the .cc .hh .py and SConscript file
follow the "gem5 tutorial - creating your first simobjec". The major code in
.hh file is：
class RMCache : public Cache
{
public：
typedef RMCacheParams Params;
RMCache(const Params *p);
~RMCache() {}
};
and major code in .cc file is：
RMCache::RMCache(const Params *p)
: Cache(p)
{
}
RMCache*
RMCacheParams::create()
{
return new RMCache(this);
}
the .py file is just as same as BaseCache.py. Re-build gem5 is OK, but when I
rum a test, I got a segment fault. I use gdb to trace, and find out it happened
in "blkSize(p->system->cacheLineSize()", and the value of the p->system is 0x0.
So it seems that the parameter isn't . But I do set it in the config scripts,
so how can i fix it?
Any help will be greatly appreciated, thanks!
Simon
[email protected]
From: Jason Lowe-Power
Date: 2016-11-21 23:11
To: gem5 users mailing list
Subject: Re: [gem5-users] simulate a racetrack memory in gem5
Hi Simon,
As far as I know there aren't any racetrack memory models for gem5.
Depending on what you're trying to implement with racetrack memory (e.g., cache
or main-memory) there are a number of examples of similar things in the
codebase. The DRAM controller is a really good example of how to make a good
model of memory (src/mem/dram_ctrl.*).
Good luck!
Jason
On Mon, Nov 21, 2016 at 8:20 AM [email protected] <[email protected]>
wrote:
Hello everyone,
I am new with gem5 simulate. I want to simulate a racetrack memory in gem5.
Is there any specific patch or turorial could help me to do that?
Thanks a lot
Simon
[email protected]
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