*Hi *
*I wrote a configuration script for a multicore system based on ARM and it
seems fine except for the workload. i wanted to try testing the
configuration by assigning a hello world executable for each CPU.*
*I tried creating different processes but I've got some indexing error then
i made a for loop like this:*
i=0
for i in xrange(np):
process = LiveProcess()
process.cmd = ['tests/test-progs/hello/bin/arm/linux/hello']
system.cpu[i].workload = process
system.cpu[i].createThreads()
*and all i get is this :*
Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (4096 Mbytes) does not match the address range
assigned (512 Mbytes)
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
0: system.remote_gdb.listener: listening for remote gdb #3 on port 7003
*it suppose to show 4 x Hello World!. i don't understand the problem!!*
*One other thing, i know that to use a multithreaded application I have to
use the m5threads, But, do I have to apply some changes to my configuration
script to support the multithreaded applications ?*
*Thank you*
*PS : Attached the configuration script*
--
*Anouar NECHI*
*IT Engineer : Industrial systemsHigher Institute of Computer Science*
import m5
from m5.objects import *
from caches import *
from optparse import OptionParser
parser = OptionParser()
parser.add_option('--l1i_size', help="L1 instruction cache size")
parser.add_option('--l1d_size', help="L1 data cache size")
parser.add_option('--l2_size', help="Unified L2 cache size")
(options, args) = parser.parse_args()
#system = System()
np = 4
system = System(cpu = [DerivO3CPU(cpu_id=i) for i in xrange(np)],
mem_mode = 'timing',
mem_ranges = [AddrRange('512MB')],
cache_line_size = 64)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# Create an L1 instruction and data cache
for i in xrange(np):
system.cpu[i].icache = L1ICache(options)
system.cpu[i].dcache = L1DCache(options)
# Connect the instruction and data caches to the CPU
system.cpu[i].icache.connectCPU(system.cpu[i].icache_port)
system.cpu[i].dcache.connectCPU(system.cpu[i].dcache_port)
# Create a memory bus, a coherent crossbar, in this case
system.l2bus = SystemXBar()
# Hook the CPU ports up to the l2bus
for i in xrange(np):
system.cpu[i].icache.connectBus(system.l2bus)
system.cpu[i].dcache.connectBus(system.l2bus)
# Create an L2 cache and connect it to the l2bus
system.l2cache = L2Cache(options)
system.l2cache.connectCPUSideBus(system.l2bus)
# Create a memory bus
system.membus = SystemXBar()
# Connect the L2 cache to the membus
system.l2cache.connectMemSideBus(system.membus)
for i in xrange(np):
system.cpu[i].createInterruptController()
# Connect the system up to the membus
system.system_port = system.membus.slave
# Create a DDR3 memory controller
system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
i=0
for i in xrange(np):
process = LiveProcess()
process.cmd = ['tests/test-progs/hello/bin/arm/linux/hello']
system.cpu[i].workload = process
system.cpu[i].createThreads()
root = Root(full_system = False, system = system)
m5.instantiate()
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
