Hi dear users, My thesis is about Timing Channel Protection in Shared DRAM_Controller for cloud processors. I want to implement the Temporal Partitioning approach (proposed in HPCA 2014 by Y. Wang and et al.) in that article they worked by DRAMSim2 as an cycle accurate DRAM simulator, but because of speed-up in simulation's time, we decided to work with gem5 native DRAM controller; but the problem is that some parameters such as Turn-Length (as a criteria for time-division multiplexing), should be set in its minimum value as following: (according to article)
Min(Turn_Length)= Tw(write_Transaction) = tCWD+tBURST+twR+tRP+tRCD. but we couldn't find tCWD in DRAMCtrl.py file to set the Turn_Length value. tCWD: Column Write Delay 1) my question is that how could we find the delay of a write_Transaction in gem5 native DRAM-Controller? (or tCWD parameter) also my second question is that in the above-mentioned article, they said that the time of refreshes for DRAM Memory are initially known; it means that we can set the Turn_Length = Tw + tRFC only on those Turns that we have refresh command. 2) so my question is that how can i understand the time of Refresh-commands in order to increase the Turn_Length parameter by tRFC. Thanks a lot due to reading my email and I appreciate any suggestion for progress. Sincerely, Ashkan Asgharzade
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