Hi everyone! I'm working under SE mode and want to send some user-defined read requests to l2 cache directly(the requests don't get through CPU or L1 cache), then, according to the responses of those user-defined read requests, I send relevant user-defined write requests to l2 cache using write-back command.To achieve those, I call Cache::CpuSidePort::recvTimingReq(PacketPtr pkt) to send read/write request to l2 cache and override Cache::CpuSidePort::schedTimingResp(PacketPtr pkt, Tick when) to get response data.It works well at beginning, but soon the system is running without any new output. I use --debug-flags=Cache command and see there is also no new output, then I use --debug-flags=DRAM command and it just prints refresh info shows that no new request come to DRAM.
I‘ve been struggling with this question for many days. If you know how to inject user-defined data request into cache, pleae help me! Thank you very much! Best wishes. Chunweiguan
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
