Hi All, I want to test DVFS functionality, so I am using the following dts file for the ARM full system simulation linux-linaro-tracking-gem5/arch/arm/boot/dts/*vexpress-v2p-ca15-* *tc1-gem5_dvfs_per_core_4cpus.dts*
Is the cache from m5term not visible because the above dts file does not have any entry for cache? Regards Rahul On Tue, Nov 17, 2015 at 6:34 PM, rahul shrivastava <rshrivasta...@gmail.com> wrote: > Hi, > > I am trying to simulate the ARM system with L1 cache. I can see in > config.ini the detailed configuration for dcache and icache, but when I > login from m5term and check the cache configuration, I don't see any cache > configured. > > lscpu output from m5term is the following > *root@gem5sim:/sys/devices/system/cpu/cpu0/cpufreq# lscpu* > * Architecture: armv7l* > * CPU(s): 4* > * Thread(s) per core: 1* > * Core(s) per socket: 1* > * CPU socket(s): 4* > > Ideally, there should be the entry for l1cache also which seems to be > missing. > The following is the command that I am using to simulate the system > > M5_PATH=$(pwd)/.. ./build/ARM/gem5.fast configs/example/fs.py -n 4 *--caches > --l1d_size=32kB --l1i_size=32kB* --cpu-type=arm_detailed -r 1 > --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux > --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dtb > --disk-image=../disks/arm-ubuntu-natty-headless.img --cpu-clock=\['1 > GHz','750 MHz','500 MHz'\] > > So, although I am giving the options to configure the cache, lscpu does > not seem to reflect it. Am I missing something in the command? > > Regards > Rahul >
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