Hello users, I'm modeling a new interconnect model using classic memory system in gem5.
My question is : when two masters M1 and M2 attempt to access a memory line simultaneously, is the coherent_xbar able to observe the M2 transaction while handeling the M1 request? After debbuging a small example of two memtest objects generating two requests at the same time, I see that the second request is handled after the recvTimingRequest functon (from the M1). This is due to the sequential implementation. Am I right? Is it the right behavior of the coherent_xbar? If so, how we can observe an interrupt while handeling an access for some master? Thanks, Fela. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
