Dear Andreas, Thank you very much for the info,
Best, On Mon, May 4, 2015 at 3:43 PM, Andreas Hansson <[email protected]> wrote: > Hi Erfan, > > The cache management instructions are currently not implemented. It > would be a great addition though. The only related instruction that is > currently supported is dzcva. If you’re interested in filling in the blanks > I’m sure there are plenty people willing to help out. > > All devices in gem5 are IO coherent, and for that reason we have a > functionally correct system also without the cache flushes. There is quite > a bunch of patches on RB that I’m about to push that also makes uncacheable > accesses snoop into the caches properly. > > I hope that provides some clarity. > > Regarding your kernel panic I’d say the best way forward is to start > digging in and debug what is happening. > > Andreas > > From: Erfan Azarkhish <[email protected]> > Reply-To: gem5 users mailing list <[email protected]> > Date: Monday, 4 May 2015 14:29 > To: gem5 users <[email protected]> > Subject: [gem5-users] Cache Flushing in FS-ARM > > Dear All, > > I am running a full-system ARM simulation > (aarch-system-2014-10/vmlinux.aarch32.ll_20131205.0-gem5). > > I intend to flush the L1 and L2 caches in my device driver. > For the L1 cache, I succeed without any problem, but for the L2 cache when > I use *outer_clean_range()*, nothing happens, and when I use > *outer_cache.flush_range()*, I get a kernel fault (null pointer). > > Also, I get in the messages that the following instructions are not > implemented: > warn: instruction 'mcr icialluis' unimplemented > warn: instruction 'mcr dccimvac' unimplemented > warn: instruction 'mcr dccmvau' unimplemented > warn: instruction 'mcr icimvau' unimplemented > > Can anybody help me with this issue? > > Thanks in advance, > Best Regards, > > -- > Erfan Azarkhish > Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna > DEI - University of Bologna, Italy > https://www.linkedin.com/in/erfanazarkhish > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Erfan Azarkhish Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna DEI - University of Bologna, Italy https://www.linkedin.com/in/erfanazarkhish
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