Hi
I am simulating an x86 machine with 16 cores. I am using the MESI cache
coherence protocol. I have 3 doubts as follows:
*Q.1 *How to configure MSHR for L1 Instruction and Data separately.
*Q.2 *How to configure cycle access latency for L1 Instruction and Data
separately.
*Q.3* In the 2 files, I can see the settings of cache:
File: *gem5-stable/configs/common/Caches.py*
class L2Cache(RubyCache):
-
latency = 15
File: *gem5-stable/configs/ruby/MESI_Two_Level.py*
class L2Cache(BaseCache):
- assoc = 8
- hit_latency = 20
- response_latency = 20
- mshrs = 20
- tgts_per_mshr = 12
- write_buffers = 8
Which one is significant?
--
Have a great day!
Thanks and Warm Regards
Davesh Shingari
Master's in Computer Engineering [EE]
Arizona State University
[email protected]
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
