Hi all, I am running the parallel version of Dijkstra benchmark on my script which uses the O3_ARM_v7a_3 processor. Bench mark runs succesfully on se.py. However, for my script it gives the following error
gem5.opt: build/ARM/cpu/o3/rename_map.hh:120: PhysRegIndex SimpleRenameMap::lookup(SimpleRenameMap::RegIndex) const: Assertion `arch_reg < map.size()' failed Does this mean that number of physical registers in processor are not sufficient? If yes, I even tried by setting the following attribues of O3_ARM_v7a_3 as below, however I still get same error. numPhysIntRegs = 3000 numPhysFloatRegs = 3000 numPhysCCRegs=3000 Can anyone help me on this please? Thank you all for ur kind consideration. > Hi all, > > I need to run the multithreaded (pthread) version of Dijkstra benchmark on > a systemc consisting of multi-cores (say 2) of Cortex A7. > > Please note that, I compiled the source code of dijkstra bench mark with > number of processors fixed to 2. I compiled it statically with m5thread > i.e linking thread.o to the object/binary file of bench mark. > > First I run the benchmark on se.py. As I mentioned that benchmark has > number of processors fixed to 2. When I use following command > > build/ARM/gem5.opt configs/example/se.py -n 2 -c > dijkstra_parallel_squeue_obj --options="2" > > It generates the following output with error > -------------------------------------------------------------- > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Oct 1 2014 19:17:30 > gem5 started Oct 21 2014 16:01:32 > gem5 executing on naveed-desktop > command line: build/ARM/gem5.opt configs/example/se.py -n 2 -c > dijkstra_parallel_squeue_obj --options=2 > Global frequency set at 1000000000000 ticks per second > 0: system.cpu0.isa: ISA system set to: 0 0xc41ce00 > 0: system.cpu1.isa: ISA system set to: 0 0xc41ce00 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > info: Increasing stack size by one page. > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > fatal: Called sys_clone, but no unallocated thread contexts found! > @ tick 114892000 > [cloneFunc:build/ARM/sim/syscall_emul.cc, line 859] > Memory Usage: 588688 KBytes > Program aborted at tick 114892000 > Aborted (core dumped) > > ------------------------------------------------------------- > HOWEVER, if I change number of processors on commandline option to 3, > there is no error as shown below. Can someone explains me why no error > this time? > > > -------------------------------------------------------- > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Oct 1 2014 19:17:30 > gem5 started Oct 21 2014 16:06:49 > gem5 executing on naveed-desktop > command line: build/ARM/gem5.opt configs/example/se.py -n 3 -c > dijkstra_parallel_squeue_obj --options=3 > Global frequency set at 1000000000000 ticks per second > 0: system.cpu0.isa: ISA system set to: 0 0xa9f6e00 > 0: system.cpu1.isa: ISA system set to: 0 0xa9f6e00 > 0: system.cpu2.isa: ISA system set to: 0 0xa9f6e00 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 > 0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002 > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > info: Increasing stack size by one page. > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > Shortest path is 24 in cost. Path is: 0 2 1 6 7 8 10 12 15 > Exiting @ tick 129116000 because target called exit() > ----------------------------------------------------------------- > > SECOND part of my question is that I use the following script (modified > version of se.py) to run the same dijkestra benchmark on Cortex A7. But it > gives error. I first Post here the script and then error > > -------------------------------Script--------------------------- > import optparse > import sys > import os > > import m5 > from m5.defines import buildEnv > from m5.objects import * > from m5.util import addToPath, fatal > > addToPath('../common') > addToPath('../ruby') > > import Options > import Ruby > import Simulation > import CacheConfig > import MemConfig > from Caches import * > from cpu2000 import * > from O3_ARM_v7a import * > > def get_processes(options): > """Interprets provided options and returns a list of processes""" > > multiprocesses = [] > inputs = [] > outputs = [] > errouts = [] > pargs = [] > > workloads = options.cmd.split(';') > if options.input != "": > inputs = options.input.split(';') > if options.output != "": > outputs = options.output.split(';') > if options.errout != "": > errouts = options.errout.split(';') > if options.options != "": > pargs = options.options.split(';') > > idx = 0 > for wrkld in workloads: > process = LiveProcess() > process.executable = wrkld > process.cwd = os.getcwd() > > if len(pargs) > idx: > process.cmd = [wrkld] + pargs[idx].split() > else: > process.cmd = [wrkld] > > if len(inputs) > idx: > process.input = inputs[idx] > if len(outputs) > idx: > process.output = outputs[idx] > if len(errouts) > idx: > process.errout = errouts[idx] > > multiprocesses.append(process) > idx += 1 > > if options.smt: > assert(options.cpu_type == "detailed" or options.cpu_type == > "inorder") > return multiprocesses, idx > else: > return multiprocesses, 1 > > > parser = optparse.OptionParser() > Options.addCommonOptions(parser) > Options.addSEOptions(parser) > parser.add_option("--I_Cache",type="string") > parser.add_option("--D_Cache",type="string") > > parser.add_option("--TLB_Size",type="string") > parser.add_option("--Volts",type="string") > parser.add_option("--Clocks",type="string") > > if '--ruby' in sys.argv: > Ruby.define_options(parser) > > (options, args) = parser.parse_args() > > if args: > print "Error: script doesn't take any positional arguments" > sys.exit(1) > > multiprocesses = [] > numThreads = 1 > > if options.bench: > apps = options.bench.split("-") > if len(apps) != options.num_cpus: > print "number of benchmarks not equal to set num_cpus!" > sys.exit(1) > > for app in apps: > try: > if buildEnv['TARGET_ISA'] == 'alpha': > exec("workload = %s('alpha', 'tru64', '%s')" % ( > app, options.spec_input)) > elif buildEnv['TARGET_ISA'] == 'arm': > exec("workload = %s('arm_%s', 'linux', '%s')" % ( > app, options.arm_iset, options.spec_input)) > else: > exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" > % ( > app, options.spec_input)) > multiprocesses.append(workload.makeLiveProcess()) > except: > print >>sys.stderr, "Unable to find workload for %s: %s" % ( > buildEnv['TARGET_ISA'], app) > sys.exit(1) > elif options.cmd: > multiprocesses, numThreads = get_processes(options) > else: > print >> sys.stderr, "No workload specified. Exiting!\n" > sys.exit(1) > > # Check -- do not allow SMT with multiple CPUs > if options.smt and options.num_cpus > 1: > fatal("You cannot use SMT with multiple CPUs!") > > np = options.num_cpus#reading number of processors input by user > #read Voltage domains > Volts= [] > if options.Volts!= "": > Volts = options.Volts.split(',') > #read clock domains > Clocks=[] > if options.Clocks!= "": > Clocks= options.Clocks.split(',') > #read I Cache sizes > I_Cache=[] > if options.I_Cache!= "": > I_Cache= options.I_Cache.split(',') > #read D Cache sizes > D_Cache=[] > if options.D_Cache!= "": > D_Cache= options.D_Cache.split(',') > #read TLB sizes > TLB_Size=[] > if options.TLB_Size!= "": > TLB_Size= options.TLB_Size.split(',') > > #define voltage domains based on values entered by user > VoltageDomainList= [VoltageDomain(voltage =Volts[i]) for i in xrange(np)] > > #define clock domains based on values entered by user > ClockDomainList= > [SrcClockDomain(clock=Clocks[i],voltage_domain=VoltageDomainList[i]) for i > in xrange(np)] > > #define L1 Instruction Cache list > L1ICacheList=[O3_ARM_v7a_ICache(size=I_Cache[i]) for i in xrange(np)] > #define L1 Data Cache list > L1DCacheList=[O3_ARM_v7a_DCache(size=D_Cache[i]) for i in xrange(np)] > > #define L2 TLB List > ArmTLBList=[O3_ARM_v7aWalkCache(size=TLB_Size[i]) for i in xrange(np)] > > #assign clock domains to cores > mycpu = [O3_ARM_v7a_3(cpu_id=i,clk_domain=ClockDomainList[i]) for i in > xrange(np)] > > i=0; > for cpu in mycpu:# adding caches to each core > > cpu.addTwoLevelCacheHierarchy(L1ICacheList[i],L1DCacheList[i],ArmTLBList[i]) > i=i+1 > #Craete the system with simple memory > mysystem = System( > cpu=mycpu, > mem_ranges = [AddrRange(options.mem_size)], > cache_line_size = options.cacheline_size, > physmem = SimpleMemory(), > membus = CoherentXBar(), > mem_mode = 'timing' > ) > > #connect slave port of membus with system port > mysystem.system_port=mysystem.membus.slave > #connect master port of membus with port of physical memory > mysystem.physmem.port=mysystem.membus.master > > # create the interrupt controller > for cpu in mycpu: > cpu.createInterruptController() > cpu.connectAllPorts(mysystem.membus) > > # Create a top-level voltage domain > mysystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) > # Create a source clock for the system and set the clock period > mysystem.clk_domain = SrcClockDomain(clock = > options.sys_clock,voltage_domain = mysystem.voltage_domain) > > # Sanity check > if options.fastmem: > if CPUClass != AtomicSimpleCPU: > fatal("Fastmem can only be used with atomic CPU!") > if (options.caches or options.l2cache): > fatal("You cannot use fastmem in combination with caches!") > > if options.simpoint_profile: > if not options.fastmem: > # Atomic CPU checked with fastmem option already > fatal("SimPoint generation should be done with atomic cpu and > fastmem") > if np > 1: > fatal("SimPoint generation not supported with more than one CPUs") > > for i in xrange(np): > if options.smt: > mysystem.cpu[i].workload = multiprocesses > elif len(multiprocesses) == 1: > mysystem.cpu[i].workload = multiprocesses[0] > else: > mysystem.cpu[i].workload = multiprocesses[i] > > if options.fastmem: > mysystem.cpu[i].fastmem = True > > if options.simpoint_profile: > mysystem.cpu[i].addSimPointProbe(options.simpoint_interval) > > if options.checker: > mysystem.cpu[i].addCheckerCpu() > > mysystem.cpu[i].createThreads() > > root = Root(full_system = False, system = mysystem) > # instantiate configuration > m5.instantiate() > exit_event = m5.simulate() > print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() > --------------------------------------------------------------- > > and following is the COMMAND and the ERROR which I get for this script > > > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Oct 1 2014 19:17:30 > gem5 started Oct 21 2014 16:21:08 > gem5 executing on naveed-desktop > command line: build/ARM/gem5.opt > configs/MyScripts/Stage0_PN_Mthreading_try3.py -n 3 -c > dijkstra_parallel_squeue_obj --options=3 --I_Cache=32MB,32MB,32MB > --D_Cache=32MB,32MB,32MB --TLB_Size=64MB,64MB,64MB --Volts=1mV,1mV,1mV > --Clocks=1GHz,1GHz,1GHz > Global frequency set at 1000000000000 ticks per second > 0: system.cpu0.isa: ISA system set to: 0 0xb5a0200 > 0: system.cpu1.isa: ISA system set to: 0 0xb5a0200 > 0: system.cpu2.isa: ISA system set to: 0 0xb5a0200 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 > 0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002 > info: Entering event queue @ 0. Starting simulation... > info: Increasing stack size by one page. > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > warn: User mode does not have SPSR > gem5.opt: build/ARM/cpu/o3/rename_map.hh:120: PhysRegIndex > SimpleRenameMap::lookup(SimpleRenameMap::RegIndex) const: Assertion > `arch_reg < map.size()' failed. > Program aborted at tick 194029000 > Aborted (core dumped) > > > > Please guide me guys.....Thanks to you all. > > Best Regards > Naveed Ul Mustafa > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > Naveed Ul Mustafa _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
