Yes… however your interrupt solution isn’t necessarily going to solve that
problem either. You could take an interrupt during a system call or a nested
interrupt and keeping track of that tends to get pretty ugly. I’d expect the
amount of time in sys calls the be quite low.
Ali
From: Guru Prasad <gurup...@buffalo.edu<mailto:gurup...@buffalo.edu>>
Date: Thursday, October 9, 2014 at 1:39 PM
To: Ali Saidi <ali.sa...@arm.com<mailto:ali.sa...@arm.com>>, gem5 users mailing
list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] [ARM] Interrupt handling
Thanks for the answer.
I have thought about this and implemented it earlier.
However, I realized after implementing it that this solution would lead to
system calls being unaccounted for, right?
On Thu, Oct 9, 2014 at 2:35 PM, Ali Saidi via gem5-users
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>> wrote:
The easiest way to do this is probably to only count instructions when
InUserMode() is true. You could wrap the stat accounting function in this in
the o3 commit stage and that would probably solve your problem instead of
trying to cache all sources of interrupts.
Ali
From: Guru Prasad via gem5-users
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Reply-To: Guru Prasad <gurup...@buffalo.edu<mailto:gurup...@buffalo.edu>>, gem5
users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Thursday, October 9, 2014 at 1:08 PM
To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: [gem5-users] [ARM] Interrupt handling
Hi,
I am looking to implement some custom instruction accounting.
I tried running some SPEC benchmarks at different frequencies and noticed that
the number of instructions vary across runs. I believe this is because of timer
based interrupts and thus would like to eliminate these.
To do this, I've been trying to find out where Gem5 sets the interrupt flags
and triggers the ISR jump. So far, the O3 model has a 'processInterrupts'
function that seems to cause the trap.
Is this a reasonable place to stop stat accounting?
Also, I looked into the kernel code to try and figure out how it is resetting
the IRQ flags. looking at arch/arm/kernel/entry-armv.S, I couldn't find
precisely where/what is doing this. However, searching kernel code for
local_irq_enable/local_irq_disable, I see that they seem to be writing to CPSR
with either orr #128 or bic #128. Is this how interrupts set/reset? If so, is
src/arch/arm/isa.cc setMiscReg a good place to instrument?
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