Hi Mohammad, For questions 1 and 2 :
Cache configuration can be knowed/changed in gem5_path/gem5-stable/configs/common/Caches.py This file allows you to change size, latency, cache line size, associativity... of the L1/L2 caches. By default, L1 is private and L2 is shared if you simulate a multicore architecture. Also you have the gem5_path/gem5-stable/configs/common/Options.py to know about the base configuration of the system such as number of cores, etc. that you can modify by command line when you launch a simulation. Cordialement / Best Regards SENNI Sophiane Ph.D. candidate - Microelectronics LIRMM - www.lirmm.fr Le 06/10/2014 17:36, Mohammad A Khasawneh via gem5-users a écrit : > > Hello everyone, > > I am new to gem5, and I am trying to work on the cache structure, what > I would like to do first is to run a benchmark on the base > configuration then modify it. I have a couple of questions: > > 1. How can I know the current configuration of the CPU (number of > CPUs, number and size of caches)? > > 2. How can I modify only these configurations (make L2 cache > larger/smaller)? > > 3. If I start to modify code under the src directory, is there any > method of version control so that I can retrieve a working code if > something breaks? > > 4. If I update gem5 through mercurial will my code changes be > overwritten? > > Thanks a lot, > Mohammad Khasawneh > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
