Hi All,
I am trying to model the Big-Little architecure on gem5. In this
architecture we have Cortex-A7 (with 4 crores) and Cortex-A15 (with 2
cores).
Each of 4 cores in A7 have their own (dedicated) Level 1 Cache but a
shared L2 Cache. Same is the case for cores on A15. How can I model this
scheme of A7.
I have modified the script in configs/common/O3_ARM_v7a.py by appending
following code
-----------------------------------------------------------
#define 4 cores of ARM7
arm_cores=[O3_ARM_v7a_3(cpu_id=i) for i in xrange(4)]
for cpu in arm_cores:
#add L1 Instruction and Data Cache to each core
cpu.addPrivateSplitL1Caches(O3_ARM_v7a_ICache(),O3_ARM_v7a_ICache())
#add L1 TLB to each core
cpu.ArmTLB=O3_ARM_v7aWalkCache()
-----------------------------------------------------------
Above code models only the A7 with 4 cores.
Now, my question is that how I can model L2 cache such that it is shared
among multiple cores of A7. I know we can do this by setting attribute
system.l2 to object of L2 cache. However, my desired system also includes
Cortex A15 which has its own L2 cache shared among its own cores. In other
words, L2 is not shared at system level...but both A7 and A15 have L2
Cache dedicated for them but shared among their cores.
Thanks in advance for your help
Naveed Ul Mustafa
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