Hi Biswabandan, As a “hack” this is definitely fine, and for limited topologies it will hopefully solve your problem. However, it would be nice to have a more general solution, and due to the very flexible cache topology of the gem5 memory system it is difficult to come up with a scheme that makes sense .
Andreas From: biswabandan panda <biswa....@gmail.com<mailto:biswa....@gmail.com>> Date: Tuesday, 19 August 2014 03:20 To: Andreas Hansson <andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>> Cc: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Classic memory model Hi, What if you assign the values something like this in the CacheConfig.py. L1Icache - 0, L1Dcache - 1, L2Cache - 2 L3Cache - 3 and IO cache with -1 (minus 1). I guess it's ok. On Mon, Aug 18, 2014 at 11:34 PM, Andreas Hansson <andreas.hans...@arm.com<mailto:andreas.hans...@arm.com>> wrote: Hi all, The challenge with adding a level is that it may be different depending on where you start counting. Consider CPU’s with private L1s and private L2, but a shared last-level cache. This would be the “L3” cache for the CPUs. However, for an I/O device the “L3” may be the L1 or L2 rather. Andreas From: biswabandan panda via gem5-users <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Reply-To: biswabandan panda <biswa....@gmail.com<mailto:biswa....@gmail.com>>, gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Date: Monday, 18 August 2014 18:53 To: Nizamudheen Ahmed <nizam.ah...@gmail.com<mailto:nizam.ah...@gmail.com>>, gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Classic memory model You could add a parameter say Level to identify the cache level. There is a flag named IstopLevel already implemented which distinguishes L1 cache from the MLCs and LLCs. You could add a similar one to differentiate the caches. The other way to distinguish the L1 cache is to check the assoc in the cache_impl.hh. On Mon, Aug 18, 2014 at 9:55 PM, Nizamudheen Ahmed via gem5-users <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> wrote: Hi, I would like to do L1Cache specific book-keeping in Classic Memory model. I understood that the cache is implemented in the cache_impl.hh. L1 and L2 caches are instances of Cache<TagStore>. is there a isL1DCache() equivalent API/flag in cache_impl.hh that i can use to selectively instrument the cache_impl.hh file? One obvious way i though was that... I add an additional configuration parameter to the Cache (let say is_l1d) and set that in the python script appropriately. BR/Nizam _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- thanks®ards BISWABANDAN http://www.cse.iitm.ac.in/~biswa/<http://www.cse.iitm.ac.in/%7Ebiswa/> “We might fall down, but we will never lay down. We might not be the best, but we will beat the best! We might not be at the top, but we will rise.” -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 -- thanks®ards BISWABANDAN http://www.cse.iitm.ac.in/~biswa/<http://www.cse.iitm.ac.in/%7Ebiswa/> “We might fall down, but we will never lay down. We might not be the best, but we will beat the best! We might not be at the top, but we will rise.” -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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